公开(公告)号：US20230077486A1

公开(公告)日：2023-03-16

申请号：US17473111

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Aleksandar ALEKSOV ,  Srinivas V. PIETAMBARAM ,  Leonel ARANA

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/15

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first via is through the core, where the first via comprise a conductive material, and a film over the first surface of the core, where the film is an adhesive. In an embodiment, a second via is through the film, where the second via comprises a conductive material, where the second via contacts the first via. In an embodiment, a centerline of the second via is aligned with a centerline of the first via. In an embodiment, a buildup layer is over the film.

公开(公告)号：US20220407203A1

公开(公告)日：2022-12-22

申请号：US17350169

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Aleksandar ALEKSOV

IPC: H01P3/06 ,  H01L49/02 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01P11/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to creating coaxial structures within glass package substrates. These techniques, in embodiments, may be extended to create other structures, for example capacitors within glass substrates. Other embodiments may be described and/or claimed.

公开(公告)号：US20220407199A1

公开(公告)日：2022-12-22

申请号：US17354903

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING

IPC: H01P1/20 ,  H05K1/02 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

公开(公告)号：US20220406991A1

公开(公告)日：2022-12-22

申请号：US17349653

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Neelam PRABHU GAUNKAR ,  Telesphor KAMGAING ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV

IPC: H01L43/02 ,  H01L23/13 ,  H01L23/15 ,  H01L23/473 ,  H01L23/498 ,  H01L23/66 ,  H01L27/22

Abstract: Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20220084931A1

公开(公告)日：2022-03-17

申请号：US17537406

申请日：2021-11-29

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：US20210265732A1

公开(公告)日：2021-08-26

申请号：US17317332

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Feras EID ,  Sasha N. OSTER ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV

IPC: H01Q9/04 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/52 ,  H01Q19/22

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.

公开(公告)号：US20200373261A1

公开(公告)日：2020-11-26

申请号：US16421989

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC: H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.

公开(公告)号：US20200286847A1

公开(公告)日：2020-09-10

申请号：US16646084

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. Forming a first solder resist (SR) layer on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. Forming a second solder resist (SR) layer on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20200168402A1

公开(公告)日：2020-05-28

申请号：US16605968

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Feras EID ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Thomas L. SOUNART ,  Johanna M. SWAN

IPC: H01G5/16 ,  H01G5/14 ,  H01L23/00

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a piezoelectrically actuated tunable capacitor having a variable capacitance formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. A piezoelectric actuator of the tunable capacitor includes first and second conductive electrodes and a piezoelectric layer that is positioned between the first and second conductive electrodes.