公开(公告)号：US11830768B2

公开(公告)日：2023-11-28

申请号：US17530777

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L23/5283

Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

公开(公告)号：US20230197728A1

公开(公告)日：2023-06-22

申请号：US17554791

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Eric Mattson ,  Sudarat Lee ,  Sarah Atanasov ,  Christopher J. Jezewski ,  Charles Mokhtarzadeh ,  Thoe Michaelos ,  I-Cheng Tung ,  Charles C. Kuo ,  Scott B. Clendenning ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit includes a lower and upper device portions including bodies of semiconductor material extending horizontally between first source and drain regions in a spaced-apart vertical stack. A first gate structure is around a body in the lower device portion and includes a first gate electrode and a first gate dielectric. A second gate structure is around a body in the upper device portion and includes a second gate electrode and a second gate dielectric, where the first gate dielectric is compositionally distinct from the second gate dielectric. In some embodiments, a dipole species has a first concentration in the first gate dielectric and a different second concentration in the second gate dielectric. A method of fabrication is also disclosed.

公开(公告)号：US20220352029A1

公开(公告)日：2022-11-03

申请号：US17863292

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Christopher J. Jezewski ,  Willy Rachmady ,  Rishabh Mehandru ,  Gilbert Dewey ,  Anh Phan

IPC: H01L21/8234 ,  H01L29/78

Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

公开(公告)号：US11205586B2

公开(公告)日：2021-12-21

申请号：US16651295

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Christopher J. Jezewski

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

公开(公告)号：US20210202275A1

公开(公告)日：2021-07-01

申请号：US16950630

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski

IPC: H01L21/67 ,  H01L21/683 ,  H01L23/528 ,  H01L21/3213 ,  H01J37/32

Abstract: Disclosed herein are tools and methods for subtractively patterning metals. These tools and methods may permit the subtractive patterning of metal (e.g., copper, platinum, etc.) at pitches lower than those achievable by conventional etch tools and/or with aspect ratios greater than those achievable by conventional etch tools. The tools and methods disclosed herein may be cost-effective and appropriate for high-volume manufacturing, in contrast to conventional etch tools.

公开(公告)号：US10700007B2

公开(公告)日：2020-06-30

申请号：US15925009

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US10068845B2

公开(公告)日：2018-09-04

申请号：US15126575

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Ramanan V. Chebiam ,  Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  James S. Clarke ,  John J. Plombon

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321

Abstract: Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally depositing a metal into a recess disposed in a dielectric material to form an interconnect, wherein conformally depositing the metal creates a seam or void in the deposited metal within or directly adjacent to the recess and heating the metal in the presence of a reactive gas to remove the seam or void, wherein the metal has a melting point that is greater than a melting point of copper. Other embodiments may be described and/or claimed.

公开(公告)号：US10008557B2

公开(公告)日：2018-06-26

申请号：US15342872

申请日：2016-11-03

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Kevin P. O'Brien

IPC: H01L21/00 ,  H01L23/00 ,  H01L49/02 ,  H01L23/48 ,  H01L21/768 ,  H01L23/64 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L21/4814 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

公开(公告)号：US09691716B2

公开(公告)日：2017-06-27

申请号：US15155791

申请日：2016-05-16

Applicant: INTEL CORPORATION

Inventor： Christopher J. Jezewski ,  Mauro J. Kobrinsky ,  Daniel Pantuso ,  Siddharth B. Bhingarde ,  Michael P. O'Day

IPC: H01L23/29 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

公开(公告)号：US09385082B2

公开(公告)日：2016-07-05

申请号：US14709430

申请日：2015-05-11

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Jasmeet S. Chawla

IPC: H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L23/528 ,  H01L21/02126 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.