公开(公告)号：US11283635B2

公开(公告)日：2022-03-22

申请号：US16723029

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Mona Vij

IPC: H04L9/32 ,  H04L9/08 ,  G06F21/78 ,  H04L29/06 ,  G06F12/14 ,  G06F9/455 ,  G06F16/18 ,  G06F16/23 ,  G06F11/10 ,  H04L9/06 ,  H04L41/0893 ,  H04L41/5009 ,  H04L41/5025 ,  H04L43/08 ,  H04L67/1008 ,  G06F9/54 ,  G06F21/60 ,  H04L9/00 ,  H04L41/0896 ,  H04L41/142 ,  H04L41/5051 ,  H04L67/141 ,  H04L41/14 ,  H04L47/70 ,  H04L67/12 ,  G06F8/41 ,  G06F9/38 ,  G06F9/445 ,  G06F9/48 ,  G06F9/50 ,  G06F11/34 ,  G06F21/62 ,  H04L67/10 ,  G16Y40/10

Abstract: Various approaches for memory encryption management within an edge computing system are described. In an edge computing system deployment, a computing device includes capabilities to store and manage encrypted data in memory, through processing circuitry configured to: allocate memory encryption keys according to a data isolation policy for a microservice domain, with respective keys used for encryption of respective sets of data within the memory (e.g., among different tenants or tenant groups); and, share data associated with a first microservice to a second microservice of the domain. Such sharing may be based on the communication of an encryption key, used to encrypt the data in memory, from a proxy (such as a sidecar) associated with the first microservice to a proxy associated with the second microservice; and maintaining the encrypted data within the memory, for use with the second microservice, as accessible with the communicated encryption key.

公开(公告)号：US11271994B2

公开(公告)日：2022-03-08

申请号：US16234718

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Thomas Willhalm ,  Karthik Kumar ,  Timothy Verrall

IPC: H04L29/08 ,  H04L67/1008 ,  H04L67/1021 ,  H04L67/10 ,  H04L67/61 ,  H04L67/63 ,  H04L67/00 ,  H04L67/59

Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.

公开(公告)号：US11243817B2

公开(公告)日：2022-02-08

申请号：US16369036

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Evan Custodio ,  Francesc Guim Bernat ,  Suraj Prabhakaran ,  Trevor Cooper ,  Ned M. Smith ,  Kshitij Doshi ,  Petar Torre

IPC: H04W36/00 ,  H04W8/08 ,  H04W36/14 ,  G06F9/48 ,  G06F3/06 ,  G06F12/10 ,  G06F13/40 ,  G06F9/50

Abstract: Technologies for migrating data between edge accelerators hosted on different edge locations include a device hosted on a present edge location. The device includes one or more processors to: receive a workload from a requesting device, determine one or more accelerator devices hosted on the present edge location to perform the workload, and transmit the workload to the one or more accelerator devices to process the workload. The one or more processor is further to determine whether to perform data migration from the one or more accelerator devices to one or more different edge accelerator devices hosted on a different edge location, and send, in response to a determination to perform the data migration, a request to the one or more accelerator devices on the present edge location for transformed workload data to be processed by the one or more different edge accelerator devices.

公开(公告)号：US11240155B2

公开(公告)日：2022-02-01

申请号：US16369430

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Monica Kenguva ,  Rashmin Patel

IPC: G06F15/16 ,  G06F9/54 ,  H04L29/06 ,  H04L12/803 ,  H04L12/851 ,  H04L12/26 ,  H04L12/927 ,  H04L12/813 ,  H04L29/08

Abstract: Technologies for load balancing on a network device in an edge network are disclosed. According to one embodiment, a network device receives, in the edge network, a request to access a function. The request includes one or more performance requirements. The network device identifies, as a function of an evaluation of the performance requirements and on monitored properties of each device associated with the network device, one or more of the devices to service the request. The network device selects one of the identified devices according to a load balancing policy and sends the request to the selected device.

公开(公告)号：US20220014588A1

公开(公告)日：2022-01-13

申请号：US17485040

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm

IPC: H04L29/08 ,  G06F12/0817 ,  G06F13/36 ,  G06F13/16

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).

公开(公告)号：US20220004468A1

公开(公告)日：2022-01-06

申请号：US17479267

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rita Gupta ,  Mark Schmisseur ,  Dimitrios Ziakas

IPC: G06F11/20 ,  G06F11/14 ,  G06F9/50 ,  G06F9/445 ,  G06F12/14

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

公开(公告)号：US11218538B2

公开(公告)日：2022-01-04

申请号：US16234865

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Ned Smith ,  Evan Custodio ,  Suraj Prabhkaran ,  Ignacio Astilleros Diez

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/24 ,  H04L12/14 ,  H04M15/00

Abstract: Technologies for determining a set of edge resources to offload a workload from a client compute device based on a brokering logic provided by a service provider include a device that includes circuitry that is in communication with edge resources. The circuitry is to receive a brokering logic from a service provider receive a request from a client compute device, wherein the request includes a function to be used to execute the request and one or more parameters associated with the client compute device, determine the one or more parameters, select, as a function of the one or more parameters and the brokering logic, a physical implementation to perform the function, wherein the physical implementation indicates a set of edge resources and a performance level for each edge resource of the set of edge resources, and perform, in response to a selection of the physical implementation, the request using the set of edge resources associated with the physical implementation.

公开(公告)号：US20210365199A1

公开(公告)日：2021-11-25

申请号：US17221541

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan CUSTODIO ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Slawomir Putyrski

IPC: G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14

Abstract: A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.

公开(公告)号：US11176091B2

公开(公告)日：2021-11-16

申请号：US15719639

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar

IPC: G06F17/00 ,  G06F16/13 ,  G06F16/22 ,  G06F16/178 ,  G06F16/25

Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.

公开(公告)号：US20210349512A1

公开(公告)日：2021-11-11

申请号：US17443374

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Dimitrios Ziakas ,  Rita D. Gupta

IPC: G06F1/26

Abstract: In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.