公开(公告)号：US20180293778A1

公开(公告)日：2018-10-11

申请号：US15482803

申请日：2017-04-09

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Joydeep Ray ,  Altug Koker ,  Eric G. Liskay

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80

Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.

公开(公告)号：US20180285110A1

公开(公告)日：2018-10-04

申请号：US15477022

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G06F12/0842 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/50

CPC classification number: G06F9/30123 ,  G06F9/5016 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60 ,  G09G5/363 ,  G09G5/393 ,  G09G2352/00 ,  G09G2360/08

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180284868A1

公开(公告)日：2018-10-04

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/32 ,  G06F3/01 ,  G06F11/30 ,  G06F11/07

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170229052A1

公开(公告)日：2017-08-10

申请号：US15016797

申请日：2016-02-05

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Arijit Mukhopadhyay ,  VijayKumar Donthireddy ,  Durgesh Borkar

IPC: G09G3/20

CPC classification number: G09G3/2003 ,  G06F3/1407 ,  G09G5/001 ,  G09G5/04 ,  G09G5/363 ,  G09G2340/06 ,  G09G2350/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: Embodiments provide for a graphics processing apparatus comprising a graphics processing unit having fixed point logic to convert YUV encoded image data to RGB encoded image data. In one embodiment the fixed point logic includes a set of fixed function logic circuits to compute a set of fixed point approximations of specified floating point color space conversion coefficients during the conversion of the YUV encoded image date to the RGB encoded image data.

公开(公告)号：US20240353912A1

公开(公告)日：2024-10-24

申请号：US18657176

申请日：2024-05-07

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F1/3253 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/1678 ,  G06F13/4022

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

公开(公告)号：US20230259458A1

公开(公告)日：2023-08-17

申请号：US18168157

申请日：2023-02-13

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126

CPC classification number: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0848 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

公开(公告)号：US11681349B2

公开(公告)日：2023-06-20

申请号：US17562056

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/3234 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287

CPC classification number: G06F1/3253 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/1678 ,  G06F13/4022

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

公开(公告)号：US11610564B2

公开(公告)日：2023-03-21

申请号：US17383806

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker ,  Kiran C. Veernapu ,  Erik G. Liskay

IPC: G09G5/39 ,  G06F3/14 ,  G06T1/20 ,  G09G5/393

Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

公开(公告)号：US11593269B2

公开(公告)日：2023-02-28

申请号：US17400415

申请日：2021-08-12

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US11409571B2

公开(公告)日：2022-08-09

申请号：US17205905

申请日：2021-03-18

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu

IPC: G06F9/50 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.