公开(公告)号：US20230333928A1

公开(公告)日：2023-10-19

申请号：US18212057

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Todd HINCK ,  Kuljit S. BAINS

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/1435 ,  G06F11/0784

Abstract: Techniques for storing and accessing metadata within selective dynamic random access memory (DRAM) devices are described. In one example, a dual in-line memory module (DIMM) includes a plurality of dynamic random access memory (DRAM) devices, wherein each of plurality of DRAM devices includes on-die ECC bits. At least one of the plurality of DRAM devices includes circuitry to provide access to read from and write to the on-die ECC bits of the DRAM device. The DIMM includes one or more pins to transmit metadata to and from the on-die ECC bits of the DRAM device.

公开(公告)号：US20230083193A1

公开(公告)日：2023-03-16

申请号：US17348435

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Xiaoming DU ,  Cong LI ,  Kuljit S. BAINS ,  Rajat AGARWAL ,  Murugasamy K. NACHIMUTHU ,  Maciej LAWNICZAK ,  Chao Yan TANG ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

公开(公告)号：US20220393682A1

公开(公告)日：2022-12-08

申请号：US17890500

申请日：2022-08-18

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Kuljit S. BAINS ,  Christopher P. MOZAK

IPC: H03K19/0175 ,  G06F13/40 ,  G06F13/42 ,  G11C7/22

Abstract: A system has an unmatched communication architecture for a unidirectional command bus and compensates for drift on the command bus based on data provided on a bidirectional data bus. The memory device has an oscillator to measure drift or an amount of delay for the command bus over a time interval. The memory device can return a value over the data bus to the memory controller based on the delay measured with the oscillator. Based on receiving the value, the memory controller can adjust configuration settings for communication on the command bus.

公开(公告)号：US20220229724A1

公开(公告)日：2022-07-21

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Rajat AGARWAL ,  Jongwon LEE

IPC: G06F11/10

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US20210286561A1

公开(公告)日：2021-09-16

申请号：US17336996

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Bill NALE

IPC: G06F3/06

Abstract: For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.

公开(公告)号：US20210279122A1

公开(公告)日：2021-09-09

申请号：US17317745

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Xiaoming DU ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.

公开(公告)号：US20200278906A1

公开(公告)日：2020-09-03

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Rajat AGARWAL ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US20200151070A1

公开(公告)日：2020-05-14

申请号：US16711243

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Jongwon LEE ,  Kuljit S. BAINS

IPC: G06F11/20 ,  G11C29/44 ,  G06F12/10 ,  G06F12/0875 ,  G11C11/4091

Abstract: In a memory system, a memory device has a memory array with multiple rows of memory having logical addresses mapped to their physical addresses and at least one spare row not having a logical address mapped to its physical address. A controller detects a failure of one of the multiple rows of memory (“failure row”) and executes a post package repair (PPR) mode. The controller can be internal to the memory device or external to the memory device. The memory device includes an internal scratchpad to allow transfer of data contents from the failure row to the spare row. The controller can map the logical address of the failure row from the physical address of the failure row to the physical address of the spare row, transfer data contents from the failure row to the internal scratchpad, and transfer the data contents from the internal scratchpad to the spare row.

公开(公告)号：US20180336943A1

公开(公告)日：2018-11-22

申请号：US15983009

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/409 ,  G11C16/24 ,  G11C16/10 ,  G11C7/00 ,  G11C7/08 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

公开(公告)号：US20180096719A1

公开(公告)日：2018-04-05

申请号：US15282766

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  John B. HALBERT ,  Kuljit S. BAINS

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10

CPC classification number: G11C11/40615 ,  G11C5/025 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4091 ,  G11C29/025 ,  G11C29/48

Abstract: Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response to the refresh command, the multiple memory devices initiate refresh with timing offsets relative to another of the memory devices. The timing offsets reduce the instantaneous power surge associated with all memory devices starting refresh simultaneously.