公开(公告)号：US20230223096A1

公开(公告)日：2023-07-13

申请号：US18122038

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Christopher P. MOZAK ,  Sagar SUTHRAM ,  Randy B. OSBORNE

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: Methods and apparatus for configurable ECC (error correction code) mode in DRAM. Selected memory cells in the bank arrays of a DRAM device (e.g., die) are used to store ECC bits. A DRAM device (e.g., die) is configured to operate in a first mode in which an on-die ECC engine employs selected bits in the arrays of memory cells in the DRAM banks as ECC bits to perform ECC operations and to operate in a second mode under which the ECC bits are not employed for ECC operations by the ECC engine and made available for external use by a host. In the second mode, the repurposed ECC bits may comprise RAS bits used for RAS (Reliability, Serviceability, and Availability) operations and/or metabits comprising metadata used for other operations by the host.

公开(公告)号：US20230013181A1

公开(公告)日：2023-01-19

申请号：US17944980

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS

IPC: G11C11/4096 ,  G11C11/4076

Abstract: Methods and apparatus implementing half width modes in DRAM and doubling of bank resources. DRAM devices, such as LPDDR6 SDRAM dies include multiple memory banks configured in memory groups and include I/O interface circuitry for first and second memory channels. A DRAM device may be selectively operated in a first half-width mode under which DQ lines for a partial memory channel operate as a first half-width DQ data bus. When operated in the first half-width mode, the partial memory channel is enabled to access all the memory banks on the DRAM. The DRAM device may also be selectively operated in a second half-width mode under which DQ lines for first and second partial memory channels operate as independent half-width DQ data buses. In this mode, each partial memory channel enables access to a respective portion of the memory banks.

公开(公告)号：US20230005921A1

公开(公告)日：2023-01-05

申请号：US17943038

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: H01L27/108 ,  G11C5/06

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power.

公开(公告)号：US20220262428A1

公开(公告)日：2022-08-18

申请号：US17738923

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Jongwon LEE ,  Tomer LEVY ,  Bill NALE ,  Amir Ali RADJAI

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/4096

Abstract: Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.

公开(公告)号：US20220011960A1

公开(公告)日：2022-01-13

申请号：US17485343

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Chang Kian TAN ,  Ru Yin NG ,  Saravanan SETHURAMAN ,  Kuljit S. BAINS

IPC: G06F3/06

Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

公开(公告)号：US20190139592A1

公开(公告)日：2019-05-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS ,  James A. McCALL ,  Ge Chang

IPC: G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G06F3/06 ,  G06F13/16

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

公开(公告)号：US20190036531A1

公开(公告)日：2019-01-31

申请号：US16146326

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Alexey KOSTINSKY ,  Nadav BONEN

IPC: H03K19/0175 ,  G06F13/16 ,  G06F3/06

CPC classification number: H03K19/017545 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1668 ,  Y02D10/14

Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

公开(公告)号：US20180061478A1

公开(公告)日：2018-03-01

申请号：US15282757

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： George VERGIS ,  Kuljit S. BAINS

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076

Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.

公开(公告)号：US20180025771A1

公开(公告)日：2018-01-25

申请号：US15611455

申请日：2017-06-01

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

公开(公告)号：US20180024878A1

公开(公告)日：2018-01-25

申请号：US15724222

申请日：2017-10-03

Applicant: Intel Corporation

Inventor： Debaleena DAS ,  Bill NALE ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.