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    Technologies for managing disaggregated accelerator networks based on remote direct memory access
    41.
    发明授权
    Technologies for managing disaggregated accelerator networks based on remote direct memory access 有权

    公开(公告)号：US11228539B2

    公开(公告)日：2022-01-18

    申请号：US16540807

    申请日：2019-08-14

    Applicant: Intel Corporation

    Inventor： Mrittika Ganguli ,  Sugesh Chandran ,  Parthasarathy Sarangam ,  Sujoy Sen ,  Susanne M. Balle ,  Rajesh Sankaran

    IPC: H04L12/931 ,  H04L29/12 ,  H04L12/06 ,  G06F30/34

    Abstract: Technologies for network interface controllers (NICs) include a compute sled and an accelerator sled in communication over a network. The accelerator sled configures a virtual switch endpoint associated with a remote direct memory access (RDMA) server instance that is associated with a field-programmable gate array (FPGA) of the accelerator sled. The accelerator sled updates local software defined networking (SDN) tables with a virtual tunnel associated with the virtual switch endpoint and a remote compute sled. A virtual switch of the accelerator sled switches virtual tunnel traffic from the remote compute sled to the RDMA server instance, which transfers data to or from the FPGA. The compute sled also updates a local SDN table with the virtual tunnel, and a virtual switch of the compute sled switches virtual tunnel traffic to or from the accelerator sled. Other embodiments are described and claimed.

    LOW LATENCY REMOTING TO ACCELERATORS
    42.
    发明申请
    LOW LATENCY REMOTING TO ACCELERATORS 有权

    公开(公告)号：US20210318920A1

    公开(公告)日：2021-10-14

    申请号：US17304820

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Pradeep Pappachan ,  Sujoy Sen ,  Joseph Grecco ,  Mukesh Gangadhar Bhavani Venkatesan ,  Reshma Lal

    IPC: G06F9/54

    Abstract: A method of offloading performance of a workload includes receiving, on a first computing system acting as an initiator, a first function call from a caller, the first function call to be executed by an accelerator on a second computing system acting as a target, the first computing system coupled to the second computing system by a network; determining a type of the first function call; and generating a list of parameter values of the first function call.

    Distributed storage location hinting for non-volatile memories
    44.
    发明授权
    Distributed storage location hinting for non-volatile memories 有权

    公开(公告)号：US10592162B2

    公开(公告)日：2020-03-17

    申请号：US16109606

    申请日：2018-08-22

    Applicant: Intel Corporation

    Inventor： Scott D. Peterson ,  Sujoy Sen ,  Anjaneya R. Chagam Reddy ,  Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    IPC: G06F3/06

    Abstract: Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.

    TECHNOLOGIES FOR COMPOSING A MANAGED NODE BASED ON TELEMETRY DATA
    45.
    发明申请
    TECHNOLOGIES FOR COMPOSING A MANAGED NODE BASED ON TELEMETRY DATA 审中-公开

    公开(公告)号：US20190068696A1

    公开(公告)日：2019-02-28

    申请号：US15859368

    申请日：2017-12-30

    Applicant: Intel Corporation

    Inventor： Sujoy Sen ,  Mohan J. Kumar

    IPC: H04L29/08 ,  H04L12/26 ,  H04L12/851 ,  H04L12/891 ,  H04L12/801

    Abstract: Technologies for composing a managed node based on telemetry data include communication circuitry and a compute device. The compute device is to receive resource-level telemetry data for each resource of a plurality of resources and rack-level telemetry data from each rack of a plurality of racks and a managed node composition request, which identifies at least one metric to be achieved by a managed node. In response to a receipt of the managed node composition request, the compute device is further to determine a present utilization of each resource of the plurality of resources and a present performance level of each rack of the plurality of racks, and determine a set of resources from the plurality of resources that satisfies the managed node composition request based on the resource-level and rack-level telemetry data.

    TECHNOLOGIES FOR PROVIDING ADAPTIVE DATA ACCESS REQUEST ROUTING IN A DISTRIBUTED STORAGE SYSTEM
    46.
    发明申请
    TECHNOLOGIES FOR PROVIDING ADAPTIVE DATA ACCESS REQUEST ROUTING IN A DISTRIBUTED STORAGE SYSTEM 审中-公开

    公开(公告)号：US20190042133A1

    公开(公告)日：2019-02-07

    申请号：US16023025

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Scott Peterson ,  Sujoy Sen

    IPC: G06F3/06 ,  H04L29/08

    Abstract: Technologies for providing adaptive data access request routing in a distributed storage system include a compute device. The compute device includes a redirector device to receive, from an initiator device, a request that identifies a data set to be accessed. The redirector device is also to determine, from a set of routing rules indicative of target devices associated with data sets, whether the identified data set is available in a storage server associated with the present redirector device, forward, in response to a determination that the identified data set is not available in a storage server associated with the present redirector device, the request to a target device associated with the data set in the routing rules, and send, to the initiator device, an identification of the target device associated with the data set in the routing rules. Other embodiments are also described and claimed.

    PACKET COALESCING
    47.
    发明申请
    PACKET COALESCING 审中-公开

    公开(公告)号：US20180198709A1

    公开(公告)日：2018-07-12

    申请号：US15859301

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

    IPC: H04L12/741 ,  H04L29/06 ,  H04L12/931

    CPC classification number: H04L45/74 ,  H04L49/20 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166

    Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    TECHNOLOGIES FOR SECURE ENCRYPTED EXTERNAL MEMORY FOR FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS)
    48.
    发明申请
    TECHNOLOGIES FOR SECURE ENCRYPTED EXTERNAL MEMORY FOR FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS) 审中-公开

    公开(公告)号：US20180150644A1

    公开(公告)日：2018-05-31

    申请号：US15721814

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Rahul Khanna ,  Susanne M. Balle ,  Francesc Guim Bernat ,  Sujoy Sen ,  Paul Dormitzer

    IPC: G06F21/62 ,  G06F21/76 ,  H04L9/08 ,  G06F13/16 ,  H03K19/173

    Abstract: Technologies for encrypted data access by field-programmable gate array (FPGA) user kernels include a computing device having an FPGA and an external memory device accessible by the FPGA. The FPGA includes a secure key store, a micro-encryption engine, and multiple slots for user kernels that are each identifiable with an index. A user kernel is programmed at an index and a symmetric encryption key is provisioned to the secure key store at the index. The micro encryption engine may read encrypted data from the external memory device, decrypt the encrypted data with the key associated with the index of the user kernel, and forward plain text data to the user kernel. The micro encryption engine may also receive plain text data from the user kernel, encrypt the plain text data with the key, and write the encrypted data to the external memory device. Other embodiments are described and claimed.

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