公开(公告)号：US20130203273A1

公开(公告)日：2013-08-08

申请号：US13575368

申请日：2011-01-31

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R12/72 ,  H01R43/20

CPC classification number: H01R12/721 ,  H01R12/727 ,  H01R12/737 ,  H01R13/6587 ,  H01R43/20 ,  H01R43/24 ,  Y10T29/49208

Abstract: A backplane connector including a substrate and a backplane connector set attached to the substrate. The backplane connector set includes a plurality of interconnect elements each having a conductive trace, a first contact member, and a second contact members matched to the first contact member. The first and second contact members extend beyond perimeter edges of the substrate. A plurality of conductive tie bars retain the interconnect elements in a fixed relationship prior to attachment to the substrate. Additive printing processes can be used to form the conductive traces.

Abstract translation: 背板连接器，包括衬底和附接到衬底的背板连接器组。 背板连接器组包括多个互连元件，每个互连元件具有导电迹线，第一接触元件和与第一接触元件匹配的第二接触元件。 第一和第二接触构件延伸超过衬底的周边边缘。 多个导电连接条在连接到基板之前将互连元件保持固定关系。 可以使用添加印刷工艺来形成导电迹线。

公开(公告)号：US20120062270A1

公开(公告)日：2012-03-15

申请号：US13318038

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: G01R31/26

CPC classification number: G01R31/2889 ,  G01R31/024 ,  H01L2224/16225

Abstract: Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.

Abstract translation: 用于测试晶圆级IC器件的诊断工具及其制作方法。 第一诊断工具可以包括具有多个接触焊盘的第一顺应印刷电路，其被配置为在晶片探针中的探针部件的远端和晶片级IC器件上的接触焊盘之间的第一接口处形成电互连。 多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。 在远离第一接口的位置处，在第一顺应印刷电路上印刷多个电气设备。 电气设备电耦合到导电迹线并且被配置为提供晶片级IC器件的连续性测试或功能的一个或多个。 第二诊断工具包括电耦合到专用IC测试装置的第二顺应印刷电路。 多个电气设备印刷在第二顺应印刷电路上并电耦合到专用IC器件。

公开(公告)号：US20120058653A1

公开(公告)日：2012-03-08

申请号：US13319228

申请日：2010-06-28

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R12/71

CPC classification number: G01R3/00 ,  G01R1/0491 ,  G01R1/0735 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer. A conductive material is deposited in at least a portion of the recesses to form conductive traces electrically coupling the contact members to the other circuit member.

Abstract translation: 插座组件，其在单个集成电路器件和另一个电路部件之间形成端子之间的无焊接电气互连。 插座壳体具有适于容纳单个集成电路装置的开口。 顺应印刷电路相对于插座壳体定位，以在位于开口中的单个集成电路装置上与端子电耦合。 柔性印刷电路包括印刷在固定装置表面上的电介质基层，同时在固定装置表面露出空腔。 多个接触构件形成在固定装置中的多个空腔中，并与电介质基底层耦合。 接触构件被暴露，其中柔性印刷电路从固定装置移除。 具有对应于目标电路几何形状的凹部的至少一个电介质层被印刷在电介质基底层上。 导电材料沉积在凹陷的至少一部分中以形成将接触构件电耦合到另一个电路构件的导电迹线。

公开(公告)号：US20120055701A1

公开(公告)日：2012-03-08

申请号：US13266486

申请日：2010-05-25

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K1/03 ,  B23K31/02 ,  H05K1/16 ,  H05K1/02 ,  H05K1/09

CPC classification number: H01R12/7082 ,  H01R12/57 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

Abstract translation: 一种互连组件，包括具有从第一表面延伸到第二表面的多个通孔的基底。 多个离散接触构件位于多个通孔中。 接触构件包括从第二表面可接近的近端，在第一表面上方延伸的远端，以及与位于第一表面和凹部之间的基底的接合区域接合的中间部分。 保持构件与至少一部分近端联接以将接触构件保持在通孔中。 保持构件可以由具有不同导电性的各种材料制成，从高导电性到非导电性。

公开(公告)号：US20120043667A1

公开(公告)日：2012-02-23

申请号：US13318263

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/522 ,  H01L21/50

CPC classification number: H01L24/82 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/185 ,  H01L2924/00

Abstract: A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.

Abstract translation: 用于至少一个半导体器件的封装以及用于制造封装的方法。 至少一个电介质层被选择性地印刷在半导体器件的至少一部分上，形成与多个电端子对准的第一凹槽。 在形成半导体器件上的接触部件的第一凹部中印刷导电材料。 至少一个电介质层被选择性地印刷在封装的至少一部分上以产生对应于目标电路几何形状的多个第二凹部。 导电材料印刷在第二凹槽的至少一部分中以产生电路几何形状。 电路几何形状包括电耦合到半导体器件上的电端子的多个暴露端子。

公开(公告)号：US20080057753A1

公开(公告)日：2008-03-06

申请号：US11935084

申请日：2007-11-05

Applicant: James Rathburn ,  Martin Cavegn

Inventor： James Rathburn ,  Martin Cavegn

IPC: H01R12/16

CPC classification number: H01R13/112 ,  H01R12/52 ,  H01R12/57 ,  H01R12/7082 ,  H01R13/24 ,  H01R13/2414 ,  H01R13/2435 ,  H05K3/3426

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of contact members are positioned in a plurality of the through openings. The contact members include a base portion and one or more beams. A layer is molded to the housing and the contact members to retain the contact members in the openings. A solder member is preferably coupled with an engagement feature on the base portion of the contact member.

Abstract translation: 一种电互连组件，用于将第一电路构件上的端子与第二电路构件上的端子电连接。 电互连组件包括具有在第一表面和第二表面之间延伸的多个通孔的壳体。 多个接触构件定位在多个通孔中。 接触构件包括基部和一个或多个梁。 将一层模制到壳体和接触构件以将接触构件保持在开口中。 焊料构件优选地与接触构件的基部上的接合特征耦合。

公开(公告)号：US20060116004A1

公开(公告)日：2006-06-01

申请号：US11325127

申请日：2006-01-04

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01R12/00

CPC classification number: H01R13/2435 ,  H01L2924/0002 ,  H01R12/714 ,  H01R12/85 ,  H01R13/193 ,  H01R13/2442 ,  H01R43/0249 ,  H05K7/1069 ,  H01L2924/00

Abstract: A normally closed connector apparatus for electrically connecting first and second circuit members. An electrically insulative connector housing having a first portion translatable relative to a second portion is provided. The connector housing is adapted to be positioned substantially between the first and second circuit members. A plurality of resilient contact members are retained in the first portion of the housing. The contact members have first distal ends that do not extend substantially above an upper surface of the second portion. Displacement of the second portion relative to the first portion in a translated configuration positions the first distal ends of the contact members above the upper surface of the second portion to electrically couple with the first circuit member.

Abstract translation: 一种用于电连接第一和第二电路构件的常闭连接器装置。 提供了具有相对于第二部分可平移的第一部分的电绝缘连接器壳体。 连接器壳体适于基本位于第一和第二电路构件之间。 多个弹性接触构件保持在壳体的第一部分中。 接触构件具有基本上不在第二部分的上表面上延伸的第一远端。 第二部分相对于第一部分以平移结构的位移将接触部件的第一远端定位在第二部分的上表面上方以电耦合第一电路部件。

公开(公告)号：US20050101164A1

公开(公告)日：2005-05-12

申请号：US10992170

申请日：2004-11-18

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/48 ,  H01L23/498 ,  H01R12/00 ,  H01R12/52 ,  H01R12/61 ,  H01R12/62 ,  H01R12/70 ,  H01R12/71 ,  H01R12/79 ,  H01R13/24 ,  H05K3/32 ,  H05K3/36

CPC classification number: H01R13/2414 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81898 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01R12/52 ,  H01R12/61 ,  H01R12/62 ,  H01R12/7082 ,  H01R12/714 ,  H01R12/79 ,  H01R13/2442 ,  H05K3/326 ,  H05K3/365 ,  Y10T29/49128 ,  Y10T29/49139 ,  Y10T29/49151 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.

公开(公告)号：US09196980B2

公开(公告)日：2015-11-24

申请号：US13418853

申请日：2012-03-13

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K1/00 ,  H01R12/52 ,  H01C1/14 ,  H01G4/228 ,  H01R12/70 ,  H05K7/10 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01R12/523 ,  H01C1/14 ,  H01G4/228 ,  H01R12/7082 ,  H05K1/0231 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4092 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  Y10T29/43 ,  Y10T29/49016 ,  Y10T29/49099 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49222

Abstract: A surface mount electrical interconnect adapted to provide an interface between solder balls on a BGA device and a PCB. A socket substrate is provided with a first surface, a second surface, and a plurality of openings sized and configured to receive the solder balls on the BGA device. A plurality of electrically conductive contact tabs are attached to the socket substrate so that contact tips on the contact tabs extend into the openings. The contact tips electrically couple with the BGA device when the solder balls are positioned in the openings. Vias electrically couple the contact tabs to contact pads located proximate the second surface of the socket substrate. Solder balls are bonded to the contact pads to electrically and mechanically couple the electrical interconnect to the PCB.

Abstract translation: 适于在BGA器件上的焊球和PCB之间提供界面的表面贴装电互连。 插座衬底设置有第一表面，第二表面和多个开口，其尺寸和构造用于容纳BGA器件上的焊球。 多个导电接触突片附接到插座基底，使得接触片上的接触尖端延伸到开口中。 当焊球定位在开口中时，接触尖端与BGA器件电耦合。 通孔将接触片电耦合到位于插座衬底的第二表面附近的接触垫。 焊球结合到接触焊盘，以电连接和机械耦合电互连到PCB。

公开(公告)号：US09054097B2

公开(公告)日：2015-06-09

申请号：US13266573

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/90 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16235 ,  H01L2224/81191 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.

Abstract translation: 一种用于IC器件的集成电路（IC）封装及其制造方法。 IC封装包括具有至少一个印刷柔顺层的互连组件，沿着第一主表面定位的多个第一接触构件，沿着第二主表面定位的多个第二接触构件，以及多个印刷导电迹线，电耦合 多个第一和第二接触构件。 柔性层定位成至少将第一接触构件偏压抵靠在IC器件上的端子。 包装基本上围绕IC器件和互连组件。 第二接触件可从包装外部进入。