公开(公告)号：US20060008945A1

公开(公告)日：2006-01-12

申请号：US11221597

申请日：2005-09-07

Applicant: James Cady ,  James Wilder ,  David Roper ,  James Wehrly

Inventor： James Cady ,  James Wilder ,  David Roper ,  James Wehrly

IPC: H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

公开(公告)号：US20050280135A1

公开(公告)日：2005-12-22

申请号：US11197267

申请日：2005-08-04

Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle ,  Julian Dowden

Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle ,  Julian Dowden

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例设计的两高CSP堆叠或模块中，堆叠两个CSP，其中一个CSP设置在另一个之上。 两个CSP与柔性电路连接。 在柔性电路和堆叠中的CSP之间设置一个形式标准。 形式标准可以采用许多配置，并且可以在柔性电路用于在具有两个或更多个组成CSP的堆叠模块中将CSP彼此连接的位置中使用。 例如，在包括四个CSP的堆叠模块中，在优选实施例中采用三个形式标准，尽管可以使用更少的标准。 形式标准提供导热物理形式，允许在广泛的CSP封装系列中找到许多变化的封装尺寸，同时采用标准连接柔性电路设计。

公开(公告)号：US20050263872A1

公开(公告)日：2005-12-01

申请号：US11173445

申请日：2005-07-01

Applicant: James Cady ,  James Wilder ,  David Roper ,  James Wehrly

Inventor： James Cady ,  James Wilder ,  David Roper ,  James Wehrly

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design that is disposed about the form. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance.

Abstract translation: 表格标准提供了一种物理形式，允许在广泛的CSP封装系列中发现许多变化的封装尺寸，同时采用围绕形式布置的标准连接柔性电路设计。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。

公开(公告)号：US20050146031A1

公开(公告)日：2005-07-07

申请号：US11011469

申请日：2004-12-14

Applicant: Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

Inventor： Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/48 ,  H01L29/40 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3463 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供了一种将集成电路器件安装到衬底上的系统和方法，以及用于将堆叠模块中采用该方法的系统和方法。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：US20050098873A1

公开(公告)日：2005-05-12

申请号：US11015521

申请日：2004-12-17

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/48

CPC classification number: H01L25/105 ,  H01L23/3114 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/107

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs are connected with flex circuitry. Preferably, a form standard is disposed along the lower surface of the CSPs. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules. An adhesive attaches the form standard to the flex circuitry. The adhesive preferably is laminated to the flex circuitry in a region larger than the cross section of the form standard, to leave portions of the flex circuitry with extended adhesive. Such portions, in a preferred embodiment, provide physical support for the flex circuitry in a manner devised to control the bend radius. In a preferred embodiment, the form standard will be devised of heat transference material, preferably a metal such as copper, for example.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 CSP与柔性电路连接。 优选地，形式标准沿着CSP的下表面设置。 形式标准可以采用许多配置，并且可以用于在堆叠模块中使用柔性电路将CSP彼此连接的地方。 粘合剂将表格标准附加到柔性电路。 粘合剂优选地在大于形式标准物的横截面的区域中层压到柔性电路上，以使延伸粘合剂留下柔性电路的部分。 在优选实施例中，这些部分以设计用于控制弯曲半径的方式为柔性电路提供物理支撑。 在一个优选的实施方案中，形式标准将被设计为热转移材料，优选例如铜等金属。

公开(公告)号：US20050062144A1

公开(公告)日：2005-03-24

申请号：US10963867

申请日：2004-10-12

Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。 形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。 这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。 在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

公开(公告)号：US20050041402A1

公开(公告)日：2005-02-24

申请号：US10958584

申请日：2004-10-05

Applicant: James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K1/00 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).