公开(公告)号：US20060050489A1

公开(公告)日：2006-03-09

申请号：US11255061

申请日：2005-10-19

Applicant: James Wehrly ,  Mark Wolfe ,  Paul Goodwin

Inventor： James Wehrly ,  Mark Wolfe ,  Paul Goodwin

IPC: H05K1/00

CPC classification number: H05K1/189 ,  H01L25/0652 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of its major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. A rigid substrate is configured to provide space on one side where the populated flex is disposed while in some embodiments, heat management or cooling structures are arranged on one side of the module to mitigate thermal accumulation in the module.

公开(公告)号：US20050067683A1

公开(公告)日：2005-03-31

申请号：US10978149

申请日：2004-10-29

Applicant: Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

Inventor： Russell Rapport ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Jeff Buchle

IPC: H01L21/44 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

公开(公告)号：US20050041404A1

公开(公告)日：2005-02-24

申请号：US10958934

申请日：2004-10-05

Applicant: James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  Russell Rapport ,  James Wehrly ,  Jeffrey Buchle

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。 本发明可用于各种尺寸和配置的封装，其范围从具有许多触点的较大的封装的基底元件到较小的封装，例如诸如管芯尺寸的封装（例如DSBGA）。 在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

公开(公告)号：US20070257349A1

公开(公告)日：2007-11-08

申请号：US11774846

申请日：2007-07-09

Applicant: James Wehrly ,  David Roper

Inventor： James Wehrly ,  David Roper

IPC: H01L23/02 ,  H01L23/52

CPC classification number: H05K1/147 ,  H01L23/49827 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/189 ,  H05K3/3421 ,  H05K2201/049 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.

Abstract translation: 提供了一种堆叠IC模块，包括堆叠配置的第一和第二引线封装，每个第一和第二引线封装具有多个引线沿着每个相关引线封装的至少一侧出现，并且柔性电路部分地设置在 第一和第二引线封装，其中柔性件自身折回以产生被压缩以与第一和第二引线封装的多个引线一致的弓形连接场。

公开(公告)号：US20070170561A1

公开(公告)日：2007-07-26

申请号：US11330307

申请日：2006-01-11

Applicant: James Wehrly

Inventor： James Wehrly

IPC: H01L23/02

CPC classification number: H05K1/189 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/147 ,  H05K1/182 ,  H05K3/326 ,  H05K2201/056 ,  H05K2201/091 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The present invention provides an improvement on the use of flexible circuit connectors for electrically coupling IC devices to one another in a stacked configuration by use of the flexible circuit to provide the connection of the stacked IC module to other circuits. Use of the flexible circuit as the connection of the IC module allows the flexible circuit to provide strain relief and allows stacked IC modules to be assembled with a lower profile than with previous methods. The IC module can be connected to external circuits through the flexible circuit connectors by a variety of means, including solder pads, edge connector pads, and socket connectors. This allows for IC devices to occupy less space then with previous methods, which is beneficial in modules such as memory modules with multiple, stacked memory devices.

Abstract translation: 本发明提供了使用柔性电路连接器来改进使用柔性电路将叠层IC模块连接到其它电路的层叠结构中的IC器件彼此电连接的柔性电路连接器。 使用柔性电路作为IC模块的连接允许柔性电路提供应变消除，并允许堆叠的IC模块以比以前的方法更低的轮廓组装。 IC模块可以通过各种方式通过柔性电路连接器连接到外部电路，包括焊盘，边缘连接器焊盘和插座连接器。 这允许IC器件占用较少的空间，然后使用先前的方法，这在诸如具有多个堆叠的存储器件的存储器模块的模块中是有益的。

公开(公告)号：US20070159545A1

公开(公告)日：2007-07-12

申请号：US11436946

申请日：2006-05-18

Applicant: James Wehrly ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David Roper

Inventor： James Wehrly ,  Ron Orris ,  Leland Szewerenko ,  Tim Roy ,  Julian Partridge ,  David Roper

IPC: G06F17/50 ,  H03K19/177 ,  H04N5/335 ,  H03K19/00 ,  H01L25/00 ,  H04N3/14

CPC classification number: H01L25/18 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/49175 ,  H01L2924/15311 ,  H05K1/147 ,  H05K1/189 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/055 ,  H05K2201/091 ,  H05K2201/09463 ,  H05K2201/10515 ,  H05K2201/10689

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

公开(公告)号：US20070114649A1

公开(公告)日：2007-05-24

申请号：US11626318

申请日：2007-01-23

Applicant: Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

Inventor： Julian Partridge ,  James Cady ,  James Wilder ,  David Roper ,  James Wehrly

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/3463 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method is stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder past that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.

Abstract translation: 本发明提供一种将集成电路器件安装到衬底上的系统和方法，并且采用该方法的系统和方法是堆叠模块。 封装的集成电路器件的接触焊盘基本上露出。 将包括较高温度焊膏合金的焊料施加到要安装的基板或集成电路器件上。 集成电路器件定位成与衬底的触点接触。 施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。 所形成的接头在随后的加工步骤中较少受到再熔化。 该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中公开的那些。 通常，创建的关节的轮廓较低。

公开(公告)号：US20060131716A1

公开(公告)日：2006-06-22

申请号：US11317425

申请日：2005-12-22

Applicant: James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Julian Dowden ,  Jeff Buchle

Inventor： James Cady ,  James Wilder ,  David Roper ,  James Wehrly ,  Julian Dowden ,  Jeff Buchle

IPC: H01L23/12

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

公开(公告)号：US20060091529A1

公开(公告)日：2006-05-04

申请号：US11231418

申请日：2005-09-21

Applicant: James Wehrly ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

Inventor： James Wehrly ,  James Wilder ,  Paul Goodwin ,  Mark Wolfe

IPC: H01L23/34

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.

Abstract translation: 灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。 沿柔性电路分布的触点提供模块与应用环境之间的连接。 电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。 衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。 其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。 来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

公开(公告)号：US20060033187A1

公开(公告)日：2006-02-16

申请号：US10917216

申请日：2004-08-12

Applicant: James Wilder ,  James Wehrly

Inventor： James Wilder ,  James Wehrly

IPC: H01L23/495

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2224/0401

Abstract: A rugged CSP module system and method are disclosed. In one embodiment of the present invention, a unitary mount is attached to a chip scale integrated circuit (CSP) to provide a CSP module with improved temperature cycle performance. In an exemplary system, the mount comprises a two metal layer flexible circuit attached to the CSP. Contacts are distributed along the flexible circuit for attachment to a printed circuit board (PCB). The body of the CSP then stands off from the PCB by the sum of the heights of the CSP contacts, the flex circuit, and the diameter of the contacts distributed along the flex circuit. Consequently, the forces arising from mismatched temperature coefficients of the PCB and CSP are distributed along a longer axis thus improving temperature cycle performance.

Abstract translation: 公开了一种坚固的CSP模块系统和方法。 在本发明的一个实施例中，单片机安装在芯片级集成电​​路（CSP）上，以提供具有改善的温度循环性能的CSP模块。 在示例性系统中，安装件包括连接到CSP的两个金属层柔性电路。 触点沿柔性电路分布，以连接到印刷电路板（PCB）。 CSP的主体然后通过CSP触点的高度，柔性电路和沿着柔性电路分布的触点的直径的总和从PCB脱离。 因此，由PCB和CSP的不匹配的温度系数引起的力沿较长的轴分布，从而提高温度循环性能。