公开(公告)号：US20160260693A1

公开(公告)日：2016-09-08

申请号：US14986207

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng

IPC: H01L25/10

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure is disposed on a top surface of the first molding compound. A passive device is coupled to the second RDL structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括包括第一半导体管芯的第一半导体封装。 第一模塑料围绕第一半导体模具。 第一再分配层（RDL）结构设置在第一模塑料的底表面上。 第一半导体管芯耦合到第一RDL结构。 第二再分配层（RDL）结构设置在第一模塑料的顶表面上。 无源器件耦合到第二RDL结构。

公开(公告)号：US12183723B2

公开(公告)日：2024-12-31

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US20240047427A1

公开(公告)日：2024-02-08

申请号：US18489814

申请日：2023-10-18

Applicant: MediaTek Inc.

Inventor： Yi-Lin Tsai ,  Wen-Sung Hsu ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L23/49822

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

公开(公告)号：US11854930B2

公开(公告)日：2023-12-26

申请号：US17901849

申请日：2022-09-01

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L21/563 ,  H01L24/16 ,  H01L25/0655 ,  H01L2924/3511

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US11469152B2

公开(公告)日：2022-10-11

申请号：US17035719

申请日：2020-09-29

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US11302592B2

公开(公告)日：2022-04-12

申请号：US16217016

申请日：2018-12-11

Applicant: MEDIATEK INC.

Inventor： Chi-Wen Pan ,  I-Hsuan Peng ,  Sheng-Liang Kuo ,  Yi-Jou Lin ,  Tai-Yu Chen

IPC: H01L23/16 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/03 ,  H01L23/04 ,  H01L25/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

公开(公告)号：US11171113B2

公开(公告)日：2021-11-09

申请号：US16563919

申请日：2019-09-08

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.

公开(公告)号：US10957611B2

公开(公告)日：2021-03-23

申请号：US16002138

申请日：2018-06-07

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/053 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/04 ,  H01L25/18 ,  H01L23/433 ,  H01L23/373

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

公开(公告)号：US10903198B2

公开(公告)日：2021-01-26

申请号：US16674298

申请日：2019-11-05

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  I-Hsuan Peng ,  Tzu-Hung Lin

IPC: H01L25/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

公开(公告)号：US10692789B2

公开(公告)日：2020-06-23

申请号：US15968449

申请日：2018-05-01

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.