METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE
    41.
    发明申请
    METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE 有权
    用于异步连续逼近的模拟数字转换器(ADC)架构的方法和系统

    公开(公告)号:US20140022105A1

    公开(公告)日:2014-01-23

    申请号:US13945579

    申请日:2013-07-18

    CPC classification number: H03M1/38 H03M1/06 H03M1/0682 H03M1/125 H03M1/466

    Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

    Abstract translation: 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生,并且处理任何检测到的元稳定性事件,例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分,诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器,用于针对数字输出的部分,在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。

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