公开(公告)号：US20220238548A1

公开(公告)日：2022-07-28

申请号：US17158888

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Litao Yang ,  Albert Fayrushin ,  Naveen Kaushik ,  Jian Li ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.

公开(公告)号：US20220231046A1

公开(公告)日：2022-07-21

申请号：US17714924

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L21/822

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11315877B2

公开(公告)日：2022-04-26

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210143167A1

公开(公告)日：2021-05-13

申请号：US17151344

申请日：2021-01-18

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Chet E. Carter

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

公开(公告)号：US20200168624A1

公开(公告)日：2020-05-28

申请号：US16203200

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20200066747A1

公开(公告)日：2020-02-27

申请号：US16111648

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L29/66 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US10553607B1

公开(公告)日：2020-02-04

申请号：US16111648

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Mark W. Kiehlbauch ,  Nancy M. Lomeli

IPC: H01L27/11 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/027 ,  H01L21/28

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming and removing a portion of lower-stack memory cell material that is laterally across individual bases in individual lower channel openings. Covering material is formed in a lowest portion of the individual lower channel openings to cover the individual bases of the individual lower channel openings. Upper channel openings are formed into an upper stack to the lower channel openings to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. A portion of upper-stack memory cell material that is laterally across individual bases in individual upper channel openings is formed and removed. After the removing of the portion of the upper-stack memory cell material, the covering material is removed from the interconnected channel openings. After the removing of the covering material, transistor channel material is formed in an upper portion of the interconnected channel openings. After forming the transistor channel material, upper-stack and lower-stack sacrificial material is replaced with control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is formed between the transistor channel material and the control-gate regions. Insulative charge-passage material is formed between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US12230325B2

公开(公告)日：2025-02-18

申请号：US17409300

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L21/768 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240021521A1

公开(公告)日：2024-01-18

申请号：US17812616

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Martin Jared Barclay ,  Harsh Narendrakumar Jain ,  Yiping Wang

IPC: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

公开(公告)号：US20230386575A1

公开(公告)日：2023-11-30

申请号：US17752207

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Haoyu Li ,  John D. Hopkins ,  Collin Howder ,  Adam W. Saxler

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.