公开(公告)号：US20200098636A1

公开(公告)日：2020-03-26

申请号：US16567047

申请日：2019-09-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi HARIKAI ,  Shogo OKITA ,  Noriyuki MATSUBARA ,  Hidefumi SAEKI ,  Akihiro ITOU

IPC: H01L21/78 ,  H01L21/683

Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

公开(公告)号：US20190295894A1

公开(公告)日：2019-09-26

申请号：US16280160

申请日：2019-02-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA

IPC: H01L21/78 ,  H01L21/683 ,  H01L21/66 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/02

Abstract: The method for manufacturing an element chip includes: sticking an adhesive tape having translucency to a front surface of a semiconductor wafer; measuring a position and a width of a second close contact portion in a dividing region; applying a laser beam having a beam diameter smaller than the width of the second close contact portion to the adhesive tape such that the laser beam does not protrude from the second close contact portion based on the width of the second close contact portion and the beam diameter, and forming an exposed portion; exposing the front surface to plasma with a back surface held by a dicing tape, and while protecting an element region from the plasma with an adhesive tape, etching the dividing region exposed in the exposed portion to dice the substrate into a plurality of element chips; and removing the adhesive tape remaining on the front surface.

公开(公告)号：US20180233395A1

公开(公告)日：2018-08-16

申请号：US15893999

申请日：2018-02-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Koji TAMURA ,  Akihiro ITOU ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/12 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68386

Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.

公开(公告)号：US20160240352A1

公开(公告)日：2016-08-18

申请号：US14873255

申请日：2015-10-02

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tetsuhiro IWAI ,  Shogo OKITA ,  Syouzou WATANABE

IPC: H01J37/32 ,  C23C16/458 ,  C23C16/50

CPC classification number: H01J37/3244 ,  C23C16/4586 ,  C23C16/466 ,  C23C16/50 ,  H01J37/321 ,  H01J37/32724 ,  H01L21/67109 ,  H01L21/67132 ,  H01L21/6831 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/68785

Abstract: A plasma processing apparatus performs plasma processing on a substrate held by a carrier. The carrier includes a frame disposed around the substrate and a holding sheet which holds the substrate and the frame. The plasma processing apparatus includes: a chamber; a stage which is disposed within the chamber and has an upper surface on which the carrier is mounted; a gas hole which is provided at a position of the upper surface opposing a bottom surface of the frame and through which cooling gas is supplied between the stage and the carrier; and a plasma exciting unit which generates plasma within the chamber.

Abstract translation: 等离子体处理装置对由载体保持的基板进行等离子体处理。 载体包括设置在基板周围的框架和保持基板和框架的保持板。 等离子体处理装置包括：室; 设置在所述室内并具有安装所述载体的上表面的台阶; 气体孔，其设置在与框架的底面相对的上表面的位置，冷却气体通过该气体供给到载台与载体之间; 以及在室内产生等离子体的等离子体激发单元。

公开(公告)号：US20160118284A1

公开(公告)日：2016-04-28

申请号：US14919325

申请日：2015-10-21

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tetsuhiro IWAI ,  Shogo OKITA ,  Syouzou WATANABE

IPC: H01L21/683

CPC classification number: H01J37/32522 ,  H01J37/321 ,  H01J37/32119

Abstract: A plasma processing apparatus includes: a vessel which includes a reaction chamber, atmosphere within the reaction chamber capable of being depressurized; a lower electrode which supports an object to be processed within the reaction chamber; a dielectric member which comprises a first surface and a second surface opposite to the first surface, and which closes an opening of the vessel such that the first surface opposes an outside of the reaction chamber and the second surface opposes the object to be processed; and a coil which opposes the first surface of the dielectric member, and which generates plasma within the reaction chamber. An electrode pattern and an insulation film which covers the electrode pattern are formed on the second surface of the dielectric member.

Abstract translation: 等离子体处理装置包括：包含反应室的容器，能够减压的反应室内的气氛; 在反应室内支撑被处理物的下电极; 介电构件，其包括第一表面和与第一表面相对的第二表面，并且封闭容器的开口，使得第一表面与反应室的外部相对，并且第二表面与待处理物体相对; 以及与电介质构件的第一表面相对并且在反应室内产生等离子体的线圈。 覆盖电极图案的电极图案和绝缘膜形成在电介质构件的第二表面上。

公开(公告)号：US20160118229A1

公开(公告)日：2016-04-28

申请号：US14865398

申请日：2015-09-25

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tetsuhiro IWAI ,  Shogo OKITA

IPC: H01J37/32

CPC classification number: H01J37/321 ,  H01J37/3211 ,  H01J37/32119

Abstract: A plasma processing apparatus includes: a vessel which includes a reaction chamber, atmosphere within the reaction chamber capable of being depressurized; a lower electrode which supports an object to be processed within the reaction chamber; a dielectric member which includes a first surface and a second surface opposite to the first surface, and which closes an opening of the vessel such that the first surface opposes an outside of the reaction chamber and the second surface opposes the object to be processed; and a coil which opposes the first surface of the dielectric member, and which generates plasma within the reaction chamber. The dielectric member has a groove formed in the first surface of the dielectric member, and at least a part of the coil is disposed in the groove.

Abstract translation: 等离子体处理装置包括：包含反应室的容器，能够减压的反应室内的气氛; 在反应室内支撑被处理物的下电极; 电介质构件，其包括第一表面和与第一表面相对的第二表面，并且封闭容器的开口，使得第一表面与反应室的外部相对，并且第二表面与待处理物体相对; 以及与电介质构件的第一表面相对并且在反应室内产生等离子体的线圈。 电介质构件具有形成在电介质构件的第一表面中的沟槽，并且线圈的至少一部分设置在沟槽中。