公开(公告)号：US20240402932A1

公开(公告)日：2024-12-05

申请号：US18753698

申请日：2024-06-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06

Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

公开(公告)号：US12105975B2

公开(公告)日：2024-10-01

申请号：US18230413

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US20240273039A1

公开(公告)日：2024-08-15

申请号：US18589259

申请日：2024-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20240146336A1

公开(公告)日：2024-05-02

申请号：US18498832

申请日：2023-10-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Alexander Hamburg ,  John Eric Linstadt ,  Evan Lawrence Erickson

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/6312 ,  H03M13/159 ,  H03M13/43

Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

公开(公告)号：US20240127882A1

公开(公告)日：2024-04-18

申请号：US18497149

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G11C11/408 ,  G06F13/42 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US11947474B2

公开(公告)日：2024-04-02

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20240079079A1

公开(公告)日：2024-03-07

申请号：US18233257

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20230377632A1

公开(公告)日：2023-11-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G11C11/4096 ,  G06F11/1048 ,  G11C7/02 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US11804259B2

公开(公告)日：2023-10-31

申请号：US17715370

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G06F11/10 ,  G06F11/1004 ,  G11C11/4076 ,  G11C2207/2263

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US11782807B2

公开(公告)日：2023-10-10

申请号：US17744347

申请日：2022-05-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/20 ,  G11C11/4093 ,  G11C29/52

CPC classification number: G06F11/2094 ,  G11C11/4093 ,  G11C29/52 ,  G06F2201/82

Abstract: A memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.