公开(公告)号：US20160276232A1

公开(公告)日：2016-09-22

申请号：US15169535

申请日：2016-05-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract translation: 半导体器件具有形成在载体上的第一互连结构。 在测试第一互连结构之后，将半导体管芯设置在第一互连结构上以使其已知良好。 半导体芯片在一个已知的好的芯片中。 在第一互连结构上形成垂直互连结构，例如凸块或凸块凸块。 分立半导体器件设置在第一互连结构或第二互连结构上。 密封剂沉积在半导体管芯，第一互连结构和垂直互连结构之上。 去除一部分密封剂以露出垂直互连结构。 第二互连结构形成在密封剂上并电连接到垂直互连结构。 第一互连结构或第二互连结构包括具有嵌入的玻璃布，玻璃交叉，填充物或纤维的绝缘层。

公开(公告)号：US20250132291A1

公开(公告)日：2025-04-24

申请号：US18492047

申请日：2023-10-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DanFeng Yang ,  Yaojian Lin ,  Linda Pei Ee Chua ,  Kai Chong Chan ,  Jian Zuo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

公开(公告)号：US20250038101A1

公开(公告)日：2025-01-30

申请号：US18357361

申请日：2023-07-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Ming-Che Hsieh ,  Linda Pei Ee Chua ,  Yaojian Lin

IPC: H01L23/50 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

Abstract: A semiconductor device has an electrical component and a plurality of e-bar structures disposed adjacent to the electrical component. An antenna interposer is disposed over a first surface of the e-bar structures. A redistribution layer is formed over a second surface of the e-bar structures opposite the first surface of the e-bar structures. The redistribution layer has a conductive layer and an insulating layer formed over the conductive layer. An encapsulant is deposited over the electrical component. The antenna interposer has a first conductive layer, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the insulating layer. The second conductive layer can be arranged as a plurality of islands or in a serpentine pattern.

公开(公告)号：US12107058B2

公开(公告)日：2024-10-01

申请号：US17445330

申请日：2021-08-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jian Zuo ,  Yaojian Lin

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/03011 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05569 ,  H01L2224/06515

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

公开(公告)号：US12080600B2

公开(公告)日：2024-09-03

申请号：US17010610

申请日：2020-09-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4857 ,  H01L21/561 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/186 ,  H01L2924/351 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/92 ,  H01L21/78 ,  H01L2224/19 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

公开(公告)号：US20240096807A1

公开(公告)日：2024-03-21

申请号：US17933149

申请日：2022-09-19

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  Hin Hwa Goh ,  Jian Zuo

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/16

CPC classification number: H01L23/5383 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/552 ,  H01L25/16 ,  H01L24/05 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.

公开(公告)号：US20230056780A1

公开(公告)日：2023-02-23

申请号：US17445330

申请日：2021-08-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Jian Zuo ,  Yaojian Lin

IPC: H01L23/00

Abstract: A semiconductor device has a semiconductor die. A first contact pad, second contact pad, and third contact pad are formed over the semiconductor die. An under-bump metallization layer (UBM) is formed over the first contact pad, second contact pad, and third contact pad. The UBM electrically connects the first contact pad to the second contact pad. The third contact pad is electrically isolated from the UBM. Conductive traces can be formed extending between the first contact pad and second contact pad under the UBM. A fourth contact pad can be formed over the first contact pad and a fifth contact pad can be formed over the second contact pad. The UBM is then formed over the fourth and fifth contact pads.

公开(公告)号：US11488932B2

公开(公告)日：2022-11-01

申请号：US16827363

申请日：2020-03-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

公开(公告)号：US11319207B2

公开(公告)日：2022-05-03

申请号：US16912902

申请日：2020-06-26

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: H01L23/31 ,  B81B7/00

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

公开(公告)号：US11127666B2

公开(公告)日：2021-09-21

申请号：US15428007

申请日：2017-02-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.