公开(公告)号：US20250006608A1

公开(公告)日：2025-01-02

申请号：US18344920

申请日：2023-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Kai Chong Chan ,  Rowena Zarate ,  Marites Roque ,  Yi Jing Eric Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

公开(公告)号：US20250132291A1

公开(公告)日：2025-04-24

申请号：US18492047

申请日：2023-10-23

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DanFeng Yang ,  Yaojian Lin ,  Linda Pei Ee Chua ,  Kai Chong Chan ,  Jian Zuo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.

公开(公告)号：US20250149454A1

公开(公告)日：2025-05-08

申请号：US18503013

申请日：2023-11-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Kai Chong Chan ,  Yaojian Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device has a first interconnect structure. A pre-molded bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the pre-molded bridge die. A second interconnect structure is disposed over the encapsulant and pre-molded bridge die. A first semiconductor die is disposed over the second interconnect structure within a footprint of the pre-molded bridge die. A second semiconductor die is disposed over the second interconnect structure within the footprint of the pre-molded bridge die.

公开(公告)号：US20250118643A1

公开(公告)日：2025-04-10

申请号：US18483433

申请日：2023-10-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yi Jing Eric Chong ,  Marites Roque ,  Rowena Zarate ,  Linda Pei Ee Chua ,  Kai Chong Chan

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.

公开(公告)号：US20250087545A1

公开(公告)日：2025-03-13

申请号：US18462612

申请日：2023-09-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Kai Chong Chan ,  Linda Pei Ee Chua ,  Yung Kuan Hsiao ,  Beng Yee Teh’ ,  Jian Zuo ,  Yaojian Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor device has a pre-molded discrete electrical component and a first encapsulant deposited over the pre-molded discrete electrical component. A first conductive layer is formed over the first encapsulant and pre-molded discrete electrical component. An electrical component is disposed over the first conductive layer. A second encapsulant is deposited over the electrical component and first conductive layer. A second conductive layer is formed over the second encapsulant. A conductive pillar is formed between the first conductive layer and second conductive layer through the second encapsulant. The pre-molded discrete electrical component has a discrete component and a third encapsulant deposited around the discrete component. The discrete component has an electrical terminal, a finish formed over the electrical terminal, and a third conductive layer formed over the finish. An interconnect structure formed on the electrical component is oriented toward the first conductive layer or the second conductive layer.