公开(公告)号：US11275528B2

公开(公告)日：2022-03-15

申请号：US16891457

申请日：2020-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G06F3/06

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US11227660B2

公开(公告)日：2022-01-18

申请号：US17016572

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Minsu Kim ,  Hyun-Wook Park ,  Bongsoon Lim

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G11C16/30

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.

公开(公告)号：US11227659B2

公开(公告)日：2022-01-18

申请号：US17021648

申请日：2020-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoon Lim ,  Jung-Yun Yun ,  Ji-Suk Kim ,  Sang-Won Park

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

公开(公告)号：US11158379B2

公开(公告)日：2021-10-26

申请号：US16935535

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10 ,  G11C7/22 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11556

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US11069417B2

公开(公告)日：2021-07-20

申请号：US16940935

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Bongsoon Lim ,  Yonghyuk Choi

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/32 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

公开(公告)号：US20210096967A1

公开(公告)日：2021-04-01

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US20210065806A1

公开(公告)日：2021-03-04

申请号：US16935535

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jae-Duk Yu ,  Kang-Bin Lee ,  Sang-Won Shim ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US10685713B2

公开(公告)日：2020-06-16

申请号：US16163968

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Jin-Young Kim ,  Kuihan Ko ,  Han Il Park ,  Bongsoon Lim

IPC: G11C16/04 ,  G11C16/14 ,  G06F3/06

Abstract: A storage device includes a nonvolatile memory device that includes memory blocks, each including memory cells, and a controller that receives a first write request from an external host device. Depending on the first write request, the controller transmits a first sanitize command to the nonvolatile memory device and transmits first write data and a first write command associated with the first write request to the nonvolatile memory device. The nonvolatile memory device is configured to sanitize first data previously written to first memory cells of a first memory block of the memory blocks in response to the first sanitize command. The nonvolatile memory device is further configured to write the first write data to second memory cells of the first memory block in response to the first write command.