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    Non-volatile memory device including multi-stack memory block and operating method thereof
    41.
    发明授权
    Non-volatile memory device including multi-stack memory block and operating method thereof 有权

    公开(公告)号：US12147666B2

    公开(公告)日：2024-11-19

    申请号：US18052428

    申请日：2022-11-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yohan Lee ,  Jaeduk Yu ,  Jiho Cho

    IPC: G06F3/06

    Abstract: According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.

    Nonvolatile memory device having multi-stack memory block and method of operating the same
    42.
    发明授权
    Nonvolatile memory device having multi-stack memory block and method of operating the same 有权

    公开(公告)号：US12119046B2

    公开(公告)日：2024-10-15

    申请号：US18045541

    申请日：2022-10-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeduk Yu ,  Yohan Lee ,  Yonghyuk Choi ,  Jiho Cho

    IPC: G11C16/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

    CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4096

    Abstract: A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

    Non-volatile memory device
    43.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11929118B2

    公开(公告)日：2024-03-12

    申请号：US17748156

    申请日：2022-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Yohan Lee ,  Sangwon Park ,  Jaeduk Yu

    IPC: G11C16/04 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/0433 ,  G11C7/1039 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

    Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

    Memory device
    45.
    发明授权
    Memory device 有权

    公开(公告)号：US11626165B2

    公开(公告)日：2023-04-11

    申请号：US17888743

    申请日：2022-08-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

    IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory device includes a cell area including memory blocks, and a peripheral circuit area including peripheral circuits that execute an erase operation for each of the memory blocks. Each memory block includes word lines that are stacked on a substrate, channel structures penetrate through the word lines, and a source region that is disposed on the substrate and connected to the channel structures. During the erase operation in which an erase voltage is provided to the source region of a target memory block among the memory blocks, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time, and to reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first time.

    Nonvolatile memory device and method of programming in a nonvolatile memory
    46.
    发明授权
    Nonvolatile memory device and method of programming in a nonvolatile memory 有权

    公开(公告)号：US11615855B2

    公开(公告)日：2023-03-28

    申请号：US17334045

    申请日：2021-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

    MEMORY DEVICE
    47.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220093179A1

    公开(公告)日：2022-03-24

    申请号：US17234955

    申请日：2021-04-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yohan Lee ,  Sangwan Nam ,  Sangwon Park

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/08 ,  G11C16/04

    Abstract: A memory device includes memory blocks, each including memory cells, and peripheral circuits that control the memory blocks and execute an erase operation for each of the memory blocks. Each memory block includes word lines stacked on a substrate, channel structures extending perpendicular to an upper surface of the substrate and penetrating through the word lines, and a source region disposed on the substrate and connected to the channel structures. During an erase operation in which an erase voltage is input to the source region of a target memory block, the peripheral circuits reduce a voltage of a first word line from a first bias voltage to a second bias voltage at a first time and reduce a voltage of a second word line, different from the first word line, from a third bias voltage to a fourth bias voltage at a second time different from the first in time.

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