公开(公告)号：US20230259402A1

公开(公告)日：2023-08-17

申请号：US18302945

申请日：2023-04-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

CPC classification number: G06F9/5044 ,  G06F9/4887 ,  G06F11/0757 ,  G06F9/52

Abstract: Systems include data processors to process a set of image data in parallel, and thread schedulers coupled to the data processors. Each of the thread schedulers provides a respective task start signal for a respective data processor. Such systems also include a bandwidth controller coupled to one or more data processors. The bandwidth controller is configured to, for each of the data processor(s): maintain a respective token count, and determine whether to stall or propagate the respective task start signal from the respective thread scheduler to the data processor based on the respective token count. Other aspects include pattern adaptors respectively provided in the schedulers to allow mixing of multiple data patterns across blocks of data, transaction aggregators that allow re-using the same image data by multiple threads of execution while the image data remains in a given data buffer, and timers to detect failure and hang events.

公开(公告)号：US20230229610A1

公开(公告)日：2023-07-20

申请号：US18190242

申请日：2023-03-27

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F9/4881 ,  G06F13/1673 ,  G06F13/4027 ,  G06F2213/0038

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US11700396B2

公开(公告)日：2023-07-11

申请号：US17523541

申请日：2021-11-10

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

CPC classification number: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

公开(公告)号：US11681598B2

公开(公告)日：2023-06-20

申请号：US17135481

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Rajat Sagar ,  Niraj Nandan ,  Kedar Chitnis ,  Brijesh Jadav ,  Mihir Mody

IPC: G06F11/00 ,  G06F11/30 ,  G06F15/78 ,  G06F11/07

CPC classification number: G06F11/3027 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/3072 ,  G06F15/7807

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

公开(公告)号：US11615043B2

公开(公告)日：2023-03-28

申请号：US17139970

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Rajasekhar Reddy Allu ,  Brian Chae ,  Mihir Mody

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.

公开(公告)号：US11463664B2

公开(公告)日：2022-10-04

申请号：US16911579

申请日：2020-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: H04N9/04 ,  G06T3/40 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US11276134B2

公开(公告)日：2022-03-15

申请号：US16847864

申请日：2020-04-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajat Sagar ,  Shashank Dabral ,  Anthony Lell ,  Brijesh Jadav

IPC: G06T5/40 ,  G06T1/20 ,  G06T1/60 ,  G06T5/00

Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

公开(公告)号：US20210407120A1

公开(公告)日：2021-12-30

申请号：US17474489

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T7/60 ,  G06T5/00 ,  G06T7/11 ,  G06T5/40

Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.

公开(公告)号：US10908946B2

公开(公告)日：2021-02-02

申请号：US15396172

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

公开(公告)号：US20200349683A1

公开(公告)日：2020-11-05

申请号：US16930342

申请日：2020-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T5/00 ,  G06T3/00 ,  G06T5/40 ,  G06T3/40 ,  G06T7/11 ,  G06T5/20

Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.