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    Intensity Separated Local White Balance Correction
    42.
    发明公开
    Intensity Separated Local White Balance Correction 审中-公开

    公开(公告)号：US20230239585A1

    公开(公告)日：2023-07-27

    申请号：US18194762

    申请日：2023-04-03

    Applicant: Texas Instruments Incorporated

    Inventor： Gang Hua ,  Shashank Dabral ,  Mihir Narendra Mody ,  Rajasekhar Reddy Allu ,  Niraj Nandan

    IPC: G06T9/00 ,  H04N9/78

    CPC classification number: H04N23/88 ,  H04N9/78 ,  H04N23/71 ,  H04N23/76 ,  H04N23/741

    Abstract: Local automatic white balance (AWB) of wide dynamic range (WDR) images is provided. Methods and systems include collecting, by an image signal processor (ISP), statistics for local AWB from at least one wide dynamic range (WDR) image received by the ISP; generating, by a processor, based on the statistics, local gain lookup tables (LUTs), one for each color channel represented in the WDR image(s), each local gain LUT providing a correlation between gain and intensity; and storing the local gain LUTs. Further processing includes, for each of multiple pixels of a WDR image to be output calculating an intensity value, accessing the local gain LUT for the color channel corresponding to that pixel using the calculated intensity value to identify a corresponding local gain value, and applying the local gain value to that pixel.

    Local memory use for perspective transform engine
    43.
    发明授权
    Local memory use for perspective transform engine 有权

    公开(公告)号：US11537299B2

    公开(公告)日：2022-12-27

    申请号：US17233361

    申请日：2021-04-16

    Applicant: Texas Instruments Incorporated

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajasekhar Reddy Allu

    IPC: G06F3/06 ,  G06F13/28

    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

    Image data processing for multi-exposure wide dynamic range image data
    44.
    发明授权
    Image data processing for multi-exposure wide dynamic range image data 有权

    公开(公告)号：US11375131B2

    公开(公告)日：2022-06-28

    申请号：US17001398

    申请日：2020-08-24

    Applicant: Texas Instruments Incorporated

    Inventor： Shashank Dabral ,  Rajasekhar Reddy Allu

    IPC: H04N5/235 ,  H04N5/217 ,  H04N5/265 ,  H04N9/73 ,  H04N5/355

    Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.

    Image processing accelerator
    45.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US11237991B2

    公开(公告)日：2022-02-01

    申请号：US16995364

    申请日：2020-08-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

    METHODS AND APPARATUS FOR IMAGE FRAME FREEZE DETECTION
    48.
    发明申请
    METHODS AND APPARATUS FOR IMAGE FRAME FREEZE DETECTION 有权

    公开(公告)号：US20210136358A1

    公开(公告)日：2021-05-06

    申请号：US16669138

    申请日：2019-10-30

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Brian Chae ,  Mihir Mody ,  Rajasekhar Reddy Allu

    IPC: H04N17/00 ,  H04N5/14 ,  H04N7/18

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.

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