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    Semiconductor device and method for forming the same
    41.
    发明授权
    Semiconductor device and method for forming the same 有权

    公开(公告)号：US11765915B2

    公开(公告)日：2023-09-19

    申请号：US17870814

    申请日：2022-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H10B63/00 ,  H10N70/00

    CPC classification number: H10B63/80 ,  H10N70/063 ,  H10N70/826

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

    MEMORY STRUCTURE
    42.
    发明申请
    MEMORY STRUCTURE 有权

    公开(公告)号：US20230046058A1

    公开(公告)日：2023-02-16

    申请号：US17979789

    申请日：2022-11-03

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565

    Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    43.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230020564A1

    公开(公告)日：2023-01-19

    申请号：US17404934

    申请日：2021-08-17

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

    Method for manufacturing a resistive random access memory structure
    45.
    发明授权
    Method for manufacturing a resistive random access memory structure 有权

    公开(公告)号：US11538990B2

    公开(公告)日：2022-12-27

    申请号：US17371376

    申请日：2021-07-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

    Semiconductor device and method for planarizing the same
    46.
    发明授权
    Semiconductor device and method for planarizing the same 有权

    公开(公告)号：US11348805B2

    公开(公告)日：2022-05-31

    申请号：US17067409

    申请日：2020-10-09

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang ,  Chin-Chin Tsai

    IPC: H01L29/423 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/11568

    Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    47.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220102429A1

    公开(公告)日：2022-03-31

    申请号：US17084609

    申请日：2020-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE AND FABRICATION METHOD THEREOF
    50.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20250098557A1

    公开(公告)日：2025-03-20

    申请号：US18380212

    申请日：2023-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kai-Jiun Chang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: A resistive random access memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; a metal nitride layer disposed on the conductive via, wherein the metal nitride has a gradient nitrogen concentration along a thickness direction of the metal nitride layer; a resistive switching layer disposed on the metal nitride layer; and a metal oxynitride layer disposed on the resistive switching layer, wherein the metal oxynitride layer has a gradient nitrogen concentration along a thickness direction of the metal oxynitride layer.

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