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公开(公告)号：US20180350817A1
公开(公告)日：2018-12-06
申请号：US16043166
申请日：2018-07-24
Inventor： Ying-Chiao Wang , Li-Wei Feng , Chien-Ting Ho , Wen-Chieh Lu , Li-Wei Liu
IPC: H01L27/108
CPC classification number: H01L27/10885 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L27/10897
Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.
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公开(公告)号：US20180335703A1
公开(公告)日：2018-11-22
申请号：US15937825
申请日：2018-03-27
Inventor： Ying-Chiao Wang , Yu-Cheng Tung , Li-Wei Feng , Chien-Ting Ho
Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
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公开(公告)号：US20180308923A1
公开(公告)日：2018-10-25
申请号：US15927103
申请日：2018-03-21
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L27/108 , H01L29/94
CPC classification number: H01L28/82 , H01L27/10808 , H01L27/10855 , H01L28/87 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US20180226409A1
公开(公告)日：2018-08-09
申请号：US15884399
申请日：2018-01-31
Inventor： Ying-Chiao Wang , Li-Wei Feng , Chien-Ting Ho
IPC: H01L27/108
CPC classification number: H01L27/10885 , H01L27/10805 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L27/10897
Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.
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公开(公告)号：US20180197868A1
公开(公告)日：2018-07-12
申请号：US15866482
申请日：2018-01-10
Inventor： Ger-Pin Lin , Tien-Chen Chan , Shu-Yen Chan , Yung-Ming Wang , Chien-Ting Ho
IPC: H01L27/108 , H01L21/76 , H01L21/02 , H01L21/3115
CPC classification number: H01L27/10891 , H01L21/02164 , H01L21/31155 , H01L21/76 , H01L21/76224 , H01L21/76237
Abstract: A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.
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Patent Agency Ranking
公开(公告)号：US20180197865A1
公开(公告)日：2018-07-12
申请号：US15859756
申请日：2018-01-02
Inventor： Tzu-Tsen Liu , Li-Wei Feng , Chien-Ting Ho
IPC: H01L27/108 , H01L29/08 , H01L23/528 , H01L23/522 , H01L21/768 , H01L21/311
CPC classification number: H01L27/10808 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76804 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L29/0847
Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.
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公开(公告)号：US20180190659A1
公开(公告)日：2018-07-05
申请号：US15856024
申请日：2017-12-27
Inventor： Feng-Yi Chang , Chien-Ting Ho , Shih-Fang Tzou , Fu-Che Lee
IPC: H01L27/108 , H01L21/02 , H01L21/28
CPC classification number: H01L27/10855 , H01L21/02071 , H01L21/28247 , H01L27/10823 , H01L27/10876 , H01L27/10894
Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.
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公开(公告)号：US20180151666A1
公开(公告)日：2018-05-31
申请号：US15362771
申请日：2016-11-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tri-Rung Yew , Hung-Chan Lin , Li-Wei Feng , Chien-Ting Ho , Chia-Lung Chang
IPC: H01L49/02 , H01L21/311 , H01L21/3205 , H01L27/108
CPC classification number: H01L28/82 , H01L21/31111 , H01L21/32051 , H01L27/10852
Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.
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公开(公告)号：US11049863B2
公开(公告)日：2021-06-29
申请号：US15889182
申请日：2018-02-05
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Ting Ho , Ying-Chiao Wang , Yu-Ching Chen , Hui-Ling Chuang , Kuei-Hsuan Yu
IPC: H01L27/108
Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
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公开(公告)号：US10553591B2
公开(公告)日：2020-02-04
申请号：US16294934
申请日：2019-03-07
Inventor： Ying-Chiao Wang , Li-Wei Feng , Chien-Ting Ho
IPC: H01L29/76 , H01L29/94 , H01L27/108
Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.
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