公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC classification number: H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20200020693A1

公开(公告)日：2020-01-16

申请号：US16583272

申请日：2019-09-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/02

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US20190319107A1

公开(公告)日：2019-10-17

申请号：US15985730

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20190287976A1

公开(公告)日：2019-09-19

申请号：US15959291

申请日：2018-04-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC: H01L27/108 ,  H01L21/8234 ,  H01L21/02

Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US20190259762A1

公开(公告)日：2019-08-22

申请号：US16402137

申请日：2019-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L23/528 ,  H01L43/02

Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.

公开(公告)号：US10312238B2

公开(公告)日：2019-06-04

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/02 ,  H01L27/22 ,  H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US20190148382A1

公开(公告)日：2019-05-16

申请号：US15810145

申请日：2017-11-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Han-Yung Tsai ,  Tzu-Chin Wu

IPC: H01L27/108 ,  H01L21/285

CPC classification number: H01L27/10852 ,  H01L21/28556 ,  H01L27/10814 ,  H01L27/10823

Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.

公开(公告)号：US20190139959A1

公开(公告)日：2019-05-09

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US10269868B1

公开(公告)日：2019-04-23

申请号：US15818673

申请日：2017-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Hsiao-Pang Chou

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.

公开(公告)号：US09384996B2

公开(公告)日：2016-07-05

申请号：US14272672

申请日：2014-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Kun-Ju Li ,  Chang-Hung Kung ,  Yue-Han Wu ,  Chih-Chien Liu

IPC: H01L21/3105 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/3105 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法及其制造方法。 根据实施例，提供具有至少具有多个第一栅极的第一区域和具有多个第二栅极的第二区域的衬底，其中相邻的第一栅极和相邻的第二栅极由绝缘体隔开，并且顶部 绝缘体的表面具有多个凹部。 然后，在第一栅极，第二栅极和绝缘体上形成覆盖层，并填充凹部。 去除覆盖层直到达到绝缘体的顶表面，从而形成填充凹部的绝缘沉积物，其中绝缘沉积物的上表面基本上与绝缘体的顶表面对准。