公开(公告)号：US10283564B1

公开(公告)日：2019-05-07

申请号：US15807528

申请日：2017-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chao-Ching Hsieh ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

公开(公告)号：US20190123104A1

公开(公告)日：2019-04-25

申请号：US15818673

申请日：2017-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Hsiao-Pang Chou

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.

公开(公告)号：US20190115394A1

公开(公告)日：2019-04-18

申请号：US15807528

申请日：2017-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chao-Ching Hsieh ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

公开(公告)号：US10177311B1

公开(公告)日：2019-01-08

申请号：US15782836

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Ching Hsieh ,  Chih-Chien Liu ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A resistive random access memory (RRAM) cell includes a substrate, a transistor having a gate on the substrate and a source/drain region in the substrate, a first inter-layer dielectric layer covering the transistor, a contact plug disposed in the first inter-layer dielectric layer and landing on the source/drain region, a resistive material layer conformally covering a protruding upper end portion of the contact plug, and a top electrode on the resistive material layer.

公开(公告)号：US20190259762A1

公开(公告)日：2019-08-22

申请号：US16402137

申请日：2019-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L23/528 ,  H01L43/02

Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.

公开(公告)号：US10312238B2

公开(公告)日：2019-06-04

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/02 ,  H01L27/22 ,  H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US20190139959A1

公开(公告)日：2019-05-09

申请号：US15803852

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  G11C11/16 ,  H01L23/528 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.

公开(公告)号：US10269868B1

公开(公告)日：2019-04-23

申请号：US15818673

申请日：2017-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Hsiao-Pang Chou

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/51

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.