公开(公告)号：US20230207692A1

公开(公告)日：2023-06-29

申请号：US18116826

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/2822 ,  H01L21/28211

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US20230112835A1

公开(公告)日：2023-04-13

申请号：US18077168

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L23/48 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

公开(公告)号：US20210104554A1

公开(公告)日：2021-04-08

申请号：US16699474

申请日：2019-11-29

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Chung-Liang Chu ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

公开(公告)号：US10658241B2

公开(公告)日：2020-05-19

申请号：US15839769

申请日：2017-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L21/82 ,  H01L27/02 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L27/092 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.

公开(公告)号：US10374006B1

公开(公告)日：2019-08-06

申请号：US16055174

申请日：2018-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/22 ,  G11C11/16

Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.

公开(公告)号：US20190181046A1

公开(公告)日：2019-06-13

申请号：US15839769

申请日：2017-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L21/82 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.