公开(公告)号：US12087666B2

公开(公告)日：2024-09-10

申请号：US18077168

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L23/48 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L23/481 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

公开(公告)号：US12040396B2

公开(公告)日：2024-07-16

申请号：US18116826

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L21/2822 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/28211

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US11935854B2

公开(公告)日：2024-03-19

申请号：US18119266

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Sung Chiang ,  Chia-Wei Liu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L23/00 ,  H01L23/488 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L23/488 ,  H01L23/53228 ,  H01L25/0655

Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.

公开(公告)号：US11877520B2

公开(公告)日：2024-01-16

申请号：US18108003

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/02 ,  H10N50/80 ,  G11C11/16 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US20230200256A1

公开(公告)日：2023-06-22

申请号：US18108003

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US20230008792A1

公开(公告)日：2023-01-12

申请号：US17406091

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Sung Chiang ,  Chia-Wei Liu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/488 ,  H01L23/532

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.

公开(公告)号：US10714466B1

公开(公告)日：2020-07-14

申请号：US16255786

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Chih-Hsien Tang ,  Yu-Ruei Chen ,  Ya-Huei Tsai ,  Rai-Min Huang ,  Chueh-Fei Tai

IPC: H01L27/22 ,  H01L27/02 ,  G03F1/36 ,  H01L43/12 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

公开(公告)号：US20190378971A1

公开(公告)日：2019-12-12

申请号：US16029641

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L27/02 ,  G11C11/16

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US10355048B1

公开(公告)日：2019-07-16

申请号：US15920008

申请日：2018-03-13

Applicant: United Microelectronics Corp.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L21/76 ,  H01L29/78 ,  G11C11/16 ,  H01L29/06 ,  H01L21/762 ,  H01L43/12 ,  H01L43/02 ,  H01L21/3205 ,  H01F10/32 ,  H01L43/08

Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.

公开(公告)号：US12268098B2

公开(公告)日：2025-04-01

申请号：US18528707

申请日：2023-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.