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公开(公告)号：US20130229856A1
公开(公告)日：2013-09-05
申请号：US13858482
申请日：2013-04-08
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
IPC: G11C7/22
CPC classification number: G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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公开(公告)号：US20130135920A1
公开(公告)日：2013-05-30
申请号：US13658697
申请日：2012-10-23
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
IPC: G11C11/21
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
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公开(公告)号：US11011226B2
公开(公告)日：2021-05-18
申请号：US16838423
申请日：2020-04-02
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US10971224B2
公开(公告)日：2021-04-06
申请号：US16886330
申请日：2020-05-28
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
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45.发明申请公开(公告)号：US20200335144A1
公开(公告)日：2020-10-22
申请号：US16869816
申请日：2020-05-08
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Seow Fong Lim , Chang Hua Siau
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
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Patent Agency Ranking
46.发明申请公开(公告)号：US20200303005A1
公开(公告)日：2020-09-24
申请号：US16838423
申请日：2020-04-02
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US10672467B2
公开(公告)日：2020-06-02
申请号：US16460708
申请日：2019-07-02
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
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48.发明申请公开(公告)号：US20200013460A1
公开(公告)日：2020-01-09
申请号：US16511205
申请日：2019-07-15
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US10074420B2
公开(公告)日：2018-09-11
申请号：US15706342
申请日：2017-09-15
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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公开(公告)号：US09997241B2
公开(公告)日：2018-06-12
申请号：US15652148
申请日：2017-07-17
Applicant: Unity Semiconductor Corporation
Inventor： Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
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