公开(公告)号：US06423579B2

公开(公告)日：2002-07-23

申请号：US09836591

申请日：2001-04-16

Applicant: Tongbi Jiang ,  Walter L. Moden

Inventor： Tongbi Jiang ,  Walter L. Moden

IPC: H01L2144

CPC classification number: H01L24/32 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3025 ,  Y10T29/49128 ,  Y10T29/49146 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention is directed toward apparatus and methods for providing substrate structures having metallic layers for microelectronics devices. In one embodiment of the invention, an apparatus includes a substrate layer, and a metallic layer attached to the substrate layer, the metallic layer being attachable to a bottom surface of the microelectronics device. The metallic layer may advantageously provide a surface free from voids or irregularities for improved attachment of microelectronics devices. The metallic layer may also provide improved conduction of thermal energy away from the device, shielding from electromagnetic interference, a vapor barrier between the device and the substrate, and may serve as a convenient ground channel. In one embodiment, the metallic layer may be continuous layer. Alternately, the metallic layer may be segmented into a plurality of closely-fitted pieces, or a plurality of spaced-apart pieces separated by expansion joints. In another embodiment, an apparatus may include a second metallic layer formed on the substrate layer opposite from the first metallic layer. In a further embodiment, a plating layer is formed on the second metallic layer. In yet another embodiment, a microelectronics package includes a substrate layer, a metallic layer attached to the substrate layer, an attachment layer formed on at least part of the metallic layer, and a die having a bottom surface attached to the attachment layer. The attachment layer may be an adhesive layer, or alternately, a eutectic layer.

Abstract translation: 本发明涉及用于提供具有用于微电子器件的金属层的衬底结构的装置和方法。 在本发明的一个实施例中，一种装置包括衬底层和附着到衬底层的金属层，该金属层可附接到微电子器件的底表面。 金属层可以有利地提供没有空隙或不规则性的表面，以改善微电子器件的附着。 金属层还可以提供远离器件的热能的改善的传导，屏蔽电磁干扰，器件和衬底之间的蒸气阻挡层，并且可以用作方便的接地通道。 在一个实施例中，金属层可以是连续层。 或者，金属层可以被分割成多个紧密配合的片，或者由膨胀节分开的多个间隔开的片。 在另一个实施例中，装置可以包括形成在与第一金属层相对的基底层上的第二金属层。 在另一实施例中，在第二金属层上形成镀层。 在另一个实施例中，微电子封装包括衬底层，附着到衬底层的金属层，形成在金属层的至少一部分上的附着层和连接到附着层的底表面的管芯。 附着层可以是粘合剂层，或者可以是共晶层。

公开(公告)号：US06410406B1

公开(公告)日：2002-06-25

申请号：US09660782

申请日：2000-09-13

Applicant: Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

Inventor： Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

IPC: H01L2146

CPC classification number: H01L24/11 ,  H01L23/485 ,  H01L24/02 ,  H01L24/45 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal. Preferably, an electrically conductive material is disposed between the bond pad and the terminal to establish an electrically conductive bond between the semiconductor device and the carrier substrate.

Abstract translation: 一种垂直安装的半导体器件，包括设置在其边缘上的至少一个接合焊盘。 接合焊盘包括设置在其上的导电凸块。 半导体器件还可以包括保护性外涂层。 本发明还包括一种制造半导体器件的方法，包括在半导体晶片中形成断开的凹口，将电路迹线重定向到每个凹口中，以及沿着凹口将晶片分离，以在所得半导体器件的边缘上形成接合焊盘 。 将半导体器件附接到载体衬底的方法包括使半导体器件定向，使得接合焊盘与载体衬底的相应端子对准，并且在焊盘和端子之间建立电连接。 优选地，导电材料设置在接合焊盘和端子之间，以在半导体器件和载体衬底之间建立导电接合。

公开(公告)号：US06380631B2

公开(公告)日：2002-04-30

申请号：US09872221

申请日：2001-05-31

Applicant: Leonard E. Mess ,  David J. Corisis ,  Walter L. Moden ,  Larry D. Kinsman

Inventor： Leonard E. Mess ,  David J. Corisis ,  Walter L. Moden ,  Larry D. Kinsman

IPC: H01L2348

CPC classification number: H01L22/26 ,  H01L23/055 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die. In an alternate embodiment, the packaging substrate comprises an electrically conductive substrate and an electrically insulative material is formed between the conductive leads and the packaging substrate. In another embodiment, the first bond pads are electrically coupled to the conductive leads by wire-bonding. Alternately, the first bond pads are in direct contact with the conductive leads in a flip chip arrangement. In another embodiment, the die is sealed within an encapsulating layer to protect the first and second die.

Abstract translation: 包装和测试模具的装置和方法 在一个实施例中，堆叠的管芯封装包括具有设置在其中的凹部的第一表面和与其连接的多个导电引线的封装衬底，第一管芯附接到凹部内的封装衬底，并且具有多个第一接合焊盘， 耦合到至少一些导电引线，以及附接到第一管芯的第二管芯，并且具有电耦合到至少一些导电引线的多个第二接合焊盘。 当堆叠的管芯封装与例如电路板接合时，封装衬底的第一表面靠近电路板，使得封装衬底至少部分地包围并保护第一和第二管芯。 定制包装基材的性能和尺寸以优化模具的操作环境，包括改善热耗散和提高模具的性能。 在替代实施例中，封装衬底包括导电衬底，并且在导电引线和封装衬底之间形成电绝缘材料。 在另一个实施例中，第一接合焊盘通过引线接合电耦合到导电引线。 或者，第一接合焊盘以倒装芯片布置与导电引线直接接触。 在另一个实施例中，将管芯密封在封装层内以保护第一和第二管芯。

公开(公告)号：US06365437B2

公开(公告)日：2002-04-02

申请号：US09227869

申请日：1999-01-08

Applicant: Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

Inventor： Warren M. Farnworth ,  Larry D. Kinsman ,  Walter L. Moden

IPC: H01L2148

CPC classification number: H01L24/72 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4943 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An integrated circuit module having sockets adapted to receive direct die contact (DDC) dies. Bond pads on each DDC die is arranged such that they are displaced with respect to one another along a particular direction. Each socket of a module includes spring arms adapted to contact the bond pads so configured on the die. The socket includes multiple types of spring arms of varying lengths.

Abstract translation: 一种具有适于接收直接管芯接触（DDC）管芯的插座的集成电路模块。 每个DDC模具上的接合垫被布置成使得它们沿着特定方向相对于彼此移位。 模块的每个插座包括适于接触如此配置在模具上的接合垫的弹簧臂。 插座包括多种类型的不同长度的弹簧臂。

公开(公告)号：US06362519B1

公开(公告)日：2002-03-26

申请号：US09836067

申请日：2001-04-17

Applicant: Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

Inventor： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

IPC: H01L2302

Abstract: A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

公开(公告)号：US06331939B1

公开(公告)日：2001-12-18

申请号：US09416249

申请日：1999-10-12

Applicant: David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

Inventor： David J. Corisis ,  Jerry M. Brooks ,  Walter L. Moden

IPC: H05K111

CPC classification number: H01L24/06 ,  H01L23/3107 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements. Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board. Yet, this isolated connection should be able to be connected to an adjacent ball on a different FBGA stack above or below that particular isolated connection. This provides for a stair step connection from the bottom of the FBGA stacked array to the top. This allows IC devices to be stacked one upon the other while maintaining a unique pin out for each pin required in the stack.

Abstract translation: 公开了一种可堆叠的精细球栅阵列（FBGA）封装，其允许将一个阵列堆叠在另一阵列上。 这种可堆叠的FBGA封装被配置成使得导电元件沿着安装到FBGA的集成电路（IC）器件的外周放置。 导电元件也具有足够的尺寸，使得它们延伸超过IC器件的底表面或顶表面，包括布线互连和封装材料，因为导电元件与位于或之下的FBGA接触以形成叠层。 诸如存储器芯片的IC器件安装在形成FBGA的一部分的印刷电路板基板的第一表面上。 引线用于将IC器件连接到印刷电路板基板，并且密封剂用于将IC器件和导线元件的基体内部和外部的电线包含在IC器件中。 此外，堆叠中的FBGA上的某些引脚需要与PC板的隔离连接。 然而，这种隔离的连接应该能够连接到位于该特定隔离连接之上或之下的不同FBGA堆叠上的相邻球。 这提供了从FBGA堆叠阵列的底部到顶部的阶梯连接。 这允许IC器件彼此堆叠，同时为堆栈中所需的每个引脚保持唯一的引脚输出。

公开(公告)号：US06312977B1

公开(公告)日：2001-11-06

申请号：US09651461

申请日：2000-08-30

Applicant: Tongbi Jiang ,  Syed S. Ahmad ,  Walter L. Moden

Inventor： Tongbi Jiang ,  Syed S. Ahmad ,  Walter L. Moden

IPC: H01L2144

CPC classification number: H01L23/49513 ,  H01L23/4951 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract translation: 本发明涉及一种使用在预定图案上施加的湿膜粘合剂将引线框架附接到优质裸片，引线框架的引线指或两者的引线框架的方法。 通过将粘合剂应用于识别好的骰子，可以通过在整个晶片上施加粘合剂的过程节省时间和材料。 通过使用湿膜将引线框架连接到良好的裸片上，如果良好的芯片随后测试不可接受，则可以从良好的模具中去除引线框架以进行返工。

公开(公告)号：US06265766B1

公开(公告)日：2001-07-24

申请号：US09483483

申请日：2000-01-14

Applicant: Walter L. Moden

Inventor： Walter L. Moden

IPC: H01L2302

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/141 ,  H05K3/328 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2203/0415 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

公开(公告)号：US06232146B1

公开(公告)日：2001-05-15

申请号：US09314873

申请日：1999-05-19

Applicant: Warren M. Farnworth ,  Walter L. Moden ,  Larry D. Kinsman

Inventor： Warren M. Farnworth ,  Walter L. Moden ,  Larry D. Kinsman

IPC: H01L2144

CPC classification number: H01L23/32 ,  H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.

公开(公告)号：US06228677B1

公开(公告)日：2001-05-08

申请号：US09505214

申请日：2000-02-16

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

IPC: H01L2144

CPC classification number: H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract translation: 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。