公开(公告)号：US09781828B2

公开(公告)日：2017-10-03

申请号：US13863481

申请日：2013-04-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Issei Yamamoto ,  Yoshihito Otsubo

IPC: H05K1/02 ,  H01L25/16 ,  H05K3/28 ,  H05K3/30 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H05K1/14 ,  H05K3/00

CPC classification number: H05K1/0296 ,  H01L23/49811 ,  H01L23/49861 ,  H01L23/552 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15312 ,  H01L2924/15322 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/141 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K3/30 ,  H05K2201/1034 ,  H05K2201/10477 ,  H05K2203/1316 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/81 ,  H01L2924/00

Abstract: A module substrate includes a plurality of electronic components mounted on at least one surface of a base substrate and a columnar terminal connection substrate connected to the one surface of the base substrate on which a plurality of the electronic components are mounted. The terminal connection substrate includes a plurality of conductor portions, at least one corner of the columnar terminal connection substrate is chamfered with a flat surface and/or curved surface, and the terminal connection substrate is connected at a side surface thereof contacting the chamfered surface, to the one surface of the base substrate.

公开(公告)号：US09275263B2

公开(公告)日：2016-03-01

申请号：US12315027

申请日：2008-11-26

Applicant: Mark Drzymala

Inventor： Mark Drzymala

IPC: G06K7/10 ,  H05K1/14 ,  H05K1/18

CPC classification number: G06K7/10722 ,  G06K7/1096 ,  G06K7/1098 ,  H05K1/141 ,  H05K1/182 ,  H05K2201/10121 ,  H05K2201/10477

Abstract: A plurality of imaging modules, each including a solid-state imager mounted on an individual printed circuit board (PCB), is mounted in a reader, such as a bi-optical, dual window, point-of-transaction workstation, for capturing images along different fields of view of diverse targets useful for customer identification, customer payment validation, operator surveillance, and coded indicia. The imaging modules are individually mounted on a motherboard for individual installation at, and individual removal from, the reader.

Abstract translation: 包括安装在单独的印刷电路板（PCB）上的固态成像器的多个成像模块安装在诸如双光学双窗口交易点工作站之类的读取器中，用于捕获图像 沿用于客户识别，客户支付验证，操作员监控和编码标记的不同目标的不同领域。 成像模块分别安装在主板上，用于单独安装，并从读取器单独移除。

公开(公告)号：US20150271920A1

公开(公告)日：2015-09-24

申请号：US14220913

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jonghae KIM ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/30 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K3/303 ,  H01L23/48 ,  H01L23/5385 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/19101 ,  H05K1/0243 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/141 ,  H05K1/144 ,  H05K1/165 ,  H05K1/18 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/1003 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/1316 ,  Y10T29/4902 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.

Abstract translation: 系统和方法涉及包括第一衬底或2D无源玻璃（POG）结构的半导体封装，其具有无源部件和形成在玻璃衬底的表面上的一个或多个封装焊盘的第一组。 半导体封装还包括具有第二组一个或多个封装焊盘的第二或层压衬底，其形成在第二层压衬底的表面上。 焊球被落下，被配置为使第一组一个或多个封装焊盘与第二组一个或多个封装焊盘接触，其中第一基板或2D POG结构朝上放置在第二或层压板的表面上 基质。 印刷电路板（PCB）可以耦合到第二或层压基板的底侧。

公开(公告)号：US08913398B2

公开(公告)日：2014-12-16

申请号：US14016707

申请日：2013-09-03

Applicant: Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

Inventor： Shinji Watanabe ,  Nobuhiro Mikami ,  Junya Sato ,  Kenichiro Fujii ,  Katsumi Abe ,  Atsumasa Sawada

IPC: H05K7/00 ,  H05K3/00 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H05K3/32

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。

公开(公告)号：US20130343023A1

公开(公告)日：2013-12-26

申请号：US13920375

申请日：2013-06-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideo NAKAGOSHI ,  Yoichi TAKAGI ,  Nobuaki OGAWA ,  Hidekiyo TAKAOKA ,  Kosuke NAKANO

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L2924/0002 ,  H05K1/141 ,  H05K3/284 ,  H05K3/368 ,  H05K2201/10318 ,  H05K2201/10477 ,  H01L2924/00

Abstract: In a bond portion between an electrical conductive land and a connection terminal member, an intermetallic compound producing region in which at least a Cu—Sn-based, an M-Sn-based (M indicates Ni and/or Mn), and a Cu-M-Sn-based intermetallic compound are produced is arranged so as to be present at a connection terminal member side. In this intermetallic compound producing region, when a cross section of the bond portion is equally defined into 10 boxes in a longitudinal direction and a lateral direction to define 100 boxes in total, a ratio of the number of boxes in each of which at least two types of intermetallic compounds having different constituent elements are present to the total number of boxes other than boxes in each of which only a Sn-based metal component is present is about 70% or more.

Abstract translation: 在导电性接地部和连接端子部件之间的接合部分中，至少具有Cu-Sn系，M-Sn系（M表示Ni和/或Mn）以及Cu 制造的M-Sn系金属间化合物被配置成存在于连接端子部件侧。 在该金属间化合物的制造区域中，当将接合部分的横截面在长度方向和横向方向等同地限定为10个盒子以总共限定100个盒子时，每个盒子的至少两个 具有不同组成元素的金属间化合物的类型存在于除了盒中除了仅存在Sn基金属成分之外的盒子总数的约70％以上。

公开(公告)号：US20130182395A1

公开(公告)日：2013-07-18

申请号：US13623731

申请日：2012-09-20

Applicant: Huawei Device Co., Ltd.

Inventor： Haixing Ding ,  Guifu Xie

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H05K1/0268 ,  H05K1/0295 ,  H05K1/113 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09954 ,  H05K2201/10477 ,  H05K2203/162

Abstract: Embodiments of the present invention provide an integrated module. The integrated module includes a printed circuit board PCB and a modular device, where the modular device is mounted on the PCB; a group of front pin pads is disposed at four edges of a front surface of the PCB and the front pin pads are located around a mounted position of the modular device; and a group of bottom pin pads is disposed at four edges of a bottom surface of the PCB. Positions where the front pin pads are disposed are symmetric to positions where the bottom pin pads are disposed; and network properties of the front pin pads and those of the bottom pin pads are the same.

Abstract translation: 本发明的实施例提供一种集成模块。 集成模块包括印刷电路板PCB和模块化设备，其中模块化设备安装在PCB上; 一组前销焊盘设置在PCB的前表面的四个边缘处，并且前引脚焊盘位于模块化设备的安装位置周围; 并且一组底部销焊盘设置在PCB的底表面的四个边缘处。 配置前销垫的位置与设置底部销垫的位置对称; 并且前引脚焊盘和底部引脚焊盘的网络属性相同。

公开(公告)号：US20130118008A1

公开(公告)日：2013-05-16

申请号：US13737123

申请日：2013-01-09

Applicant: International Business Machines Corporation

Inventor： Michael Anthony Gaynes ,  Dong Gun Kam ,  Duixian Liu ,  Scott Kevin Reynolds

IPC: H05K3/30

CPC classification number: H05K3/30 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15153 ,  H01L2924/15321 ,  H05K1/0206 ,  H05K1/141 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10098 ,  H05K2201/10477 ,  Y10T29/49128 ,  Y10T29/49137 ,  H01L2924/014

Abstract: Techniques provide improved thermal interface material application in an assembly associated with an integrated circuit package. For example, an apparatus comprises an integrated circuit module, a printed circuit board, and a heat transfer device. The integrated circuit module is mounted on a first surface of the printed circuit board. The printed circuit board has at least one thermal interface material application via formed therein in alignment with the integrated circuit module. The heat transfer device is mounted on a second surface of the printed circuit board and is thermally coupled to the integrated circuit module. The second surface of the printed circuit board is opposite to the first surface of the printed circuit board.

Abstract translation: 技术在与集成电路封装相关联的组件中提供改进的热界面材料应用。 例如，一种装置包括集成电路模块，印刷电路板和传热装置。 集成电路模块安装在印刷电路板的第一表面上。 印刷电路板具有与集成电路模块对准的至少一个热界面材料施加通孔。 传热装置安装在印刷电路板的第二表面上，并且热耦合到集成电路模块。 印刷电路板的第二表面与印刷电路板的第一表面相对。

公开(公告)号：US20130098667A1

公开(公告)日：2013-04-25

申请号：US13478802

申请日：2012-05-23

Applicant: Jong In RYU ,  Yul Kyo CHUNG ,  Tae Sung JEONG

Inventor： Jong In RYU ,  Yul Kyo CHUNG ,  Tae Sung JEONG

IPC: H05K1/09

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K2201/10477 ,  H05K2203/1461 ,  H01L2924/00

Abstract: Disclosed herein is an embedded printed circuit board (PCB) including: a copper foil laminate; an internal electronic component inserted into the copper foil laminate; a first circuit pattern formed on a surface of the internal electronic component; and a second circuit pattern formed on the copper foil laminate. Since the surface space of the electronic component embedded in the substrate is utilized as a wiring space, a wiring design can be optimized, layers can be simplified, and an increase in the thickness of the substrate can be prevented.Also, malfunction of the embedded electronic component or a warping phenomenon of a PCB due to generated heat can be prevented.

Abstract translation: 本文公开了一种嵌入式印刷电路板（PCB），包括：铜箔层压板; 插入铜箔层压体中的内部电子部件; 形成在所述内部电子部件的表面上的第一电路图案; 以及形成在铜箔层叠体上的第二电路图案。 由于嵌入在基板中的电子部件的表面空间被用作布线空间，所以可以优化布线设计，可以简化层，并且可以防止基板厚度的增加。 此外，可以防止嵌入式电子部件的故障或由于发热引起的PCB翘曲现象。

公开(公告)号：US20120282787A1

公开(公告)日：2012-11-08

申请号：US13460599

申请日：2012-04-30

Applicant: Jay Stanke

Inventor： Jay Stanke

IPC: H01R12/71

CPC classification number: H05K3/3421 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/147 ,  H05K3/32 ,  H05K2201/049 ,  H05K2201/0979 ,  H05K2201/1031 ,  H05K2201/10477 ,  H05K2201/10575 ,  H05K2201/10962 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A printed board assembly includes a printed board, an electrical component, a first interconnect that electrically connects the component to the printed board, and a second interconnect that electrically connects the first interconnect to the printed board. In some examples, the second interconnect extends between the first interconnect and the same electrical contact on the printed board to which the first interconnect is electrically connected. The first and second interconnects provide an at least partially redundant electrical pathway between the component and the printed board.

Abstract translation: 印刷电路板组件包括印刷电路板，电气部件，将组件电连接到印刷电路板的第一互连以及将第一互连电连接到印刷电路板的第二互连。 在一些示例中，第二互连在第一互连和第一互连电连接到的印刷电路板上的相同电触点之间延伸。 第一和第二互连件在部件和印刷电路板之间提供至少部分冗余的电路径。

公开(公告)号：US20110314668A1

公开(公告)日：2011-12-29

申请号：US13228496

申请日：2011-09-09

Applicant: Sotaro ITO ,  Michimasa Takahashi ,  Yukinobu Mikado

Inventor： Sotaro ITO ,  Michimasa Takahashi ,  Yukinobu Mikado

IPC: H05K3/30

CPC classification number: H01L24/83 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/096 ,  H05K2201/10477 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2224/13109

Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.

Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，包括形成具有与半导体装置的尺寸基本对应的金属层的第一绝缘性树脂基板，形成第二绝缘树脂基板，形成延伸到第一绝缘树脂基板的金属层的凹部 使得金属层的表面露出，将半导体器件容纳在凹部中，使得半导体器件安装在金属层的表面上，并且在第一绝缘树脂基板上形成树脂绝缘层，使得半导体器件 容纳在凹处被覆盖。