公开(公告)号：US20210335807A1

公开(公告)日：2021-10-28

申请号：US16886570

申请日：2020-05-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Shan Li ,  Zhiliang Xia ,  Kun Zhang ,  Wenxi Zhou ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L29/417 ,  H01L21/8234

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.

公开(公告)号：US20210320124A1

公开(公告)日：2021-10-14

申请号：US17147396

申请日：2021-01-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L21/768

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A first polysilicon layer, a dielectric sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed above a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, and the dielectric sacrificial, and into the first polysilicon layer is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, and extending vertically into or through the dielectric sacrificial layer to expose part of the dielectric sacrificial layer, and a polysilicon spacer along part of a sidewall of the opening are formed. The dielectric sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers.

公开(公告)号：US20210320115A1

公开(公告)日：2021-10-14

申请号：US17084401

申请日：2020-10-29

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Linchun Wu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an insulating layer, a semiconductor layer, a memory stack including interleaved conductive layers and dielectric layers, a source contact structure extending vertically through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer, and a channel structure extending vertically through the memory stack and the semiconductor layer into the insulating layer or the source contact structure.

公开(公告)号：US20210313351A1

公开(公告)日：2021-10-07

申请号：US17353260

申请日：2021-06-21

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Wenyu Hua ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L21/033 ,  H01L27/11556 ,  H01L27/11575

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

公开(公告)号：US20210296334A1

公开(公告)日：2021-09-23

申请号：US16881168

申请日：2020-05-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong Zhang ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

公开(公告)号：US20210193676A1

公开(公告)日：2021-06-24

申请号：US16853828

申请日：2020-04-21

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhong Zhang ,  Zhongwang Sun ,  Wenxi Zhou ,  Zhiliang Xia ,  Zhi Zhang

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device is provided that can include a stack formed of word line layers and insulating layers that are alternatingly stacked over a substrate. A first staircase of a first block can be formed in the stack and extend between first array regions of the first block. A second staircase of a second block can be formed in the stack and extend between second array regions of the second block. The semiconductor device further can have a connection region that is formed in the stack between the first staircase and second staircase.

公开(公告)号：US11043506B2

公开(公告)日：2021-06-22

申请号：US16140427

申请日：2018-09-24

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zongliang Huo ,  Zhiliang Xia ,  Li Hong Xiao ,  Jun Chen

IPC: H01L27/11 ,  H01L27/11573 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/06

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a plurality of memory strings each extending vertically above the peripheral device, a semiconductor layer disposed above and in contact with the plurality of memory strings, and a shielding layer disposed between the peripheral device and the plurality of memory strings. The shielding layer includes a conduction region configured to receive a grounding voltage during operation of the 3D memory device.

公开(公告)号：US20210134824A1

公开(公告)日：2021-05-06

申请号：US17119711

申请日：2020-12-11

Applicant: Yangtze Memory Technologies Co., Ltd

Inventor： Jun CHEN ,  Zhiliang Xia ,  Li Hong Xiao

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.

公开(公告)号：US10861872B2

公开(公告)日：2020-12-08

申请号：US16402202

申请日：2019-05-02

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Wenyu Hua ,  Fandong Liu ,  Zhiliang Xia

IPC: H01L27/11582 ,  H01L23/535 ,  H01L29/08 ,  H01L29/10

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, and a staircase structure on one side of the memory stack. The 3D memory device also includes a staircase contact in the staircase structure and a plurality of dummy source structures each extending vertically through the staircase structure. The plurality of dummy source structures surround the staircase contact.

公开(公告)号：US10804283B2

公开(公告)日：2020-10-13

申请号：US16046475

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jia He ,  Haihui Huang ,  Fandong Liu ,  Yaohua Yang ,  Peizhen Hong ,  Zhiliang Xia ,  Zongliang Huo ,  Yaobin Feng ,  Baoyou Chen ,  Qingchen Cao

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L27/11582

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.