公开(公告)号：US20240077906A1

公开(公告)日：2024-03-07

申请号：US18269905

申请日：2022-01-07

Applicant: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Nan LI ,  Chao XU ,  Zhijun FAN ,  Zuoxing YANG ,  Haifeng GUO

IPC: G06F1/08 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

公开(公告)号：US20240069590A1

公开(公告)日：2024-02-29

申请号：US18236713

申请日：2023-08-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： YU-JIE LIANG

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: A clock management circuit and a clock management method are used for managing an operating clock of a processor circuit, and the processor circuit changes the level of a state signal according to an interrupt signal. The clock management circuit includes a delay circuit for delaying a wake-up interrupt to generate a delayed wake-up interrupt; and a clock control circuit for generating the operating clock according to a reference clock, generating the wake-up interrupt according to the state signal, and adjusting the frequency of the operating clock according to the delayed wake-up interrupt.

公开(公告)号：US20240061464A1

公开(公告)日：2024-02-22

申请号：US18448475

申请日：2023-08-11

Applicant: SK hynix Inc.

Inventor： Kyu Dong Hwang ,  Sang Sic YOON

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A semiconductor device includes a command pulse generation circuit configured to generate a first command pulse in synchronization with a frequency division clock and to generate a second command pulse in synchronization with an inverted frequency division clock, based on a test write command. The semiconductor device also includes an alignment data generation circuit configured to align first internal data in an in-phase manner to generate first alignment data, based on the first command pulse, and to align second internal data in an out-of-phase manner to generate second alignment data, based on the second command pulse. The semiconductor device further includes a phase detection circuit configured to determine synchronization states of a clock and the frequency division clock, based on the first alignment data and the second alignment data.

公开(公告)号：US11907156B2

公开(公告)日：2024-02-20

申请号：US17457553

申请日：2021-12-03

Applicant: STMicroelectronics France ,  STMicroelectronics (Alps) SAS

Inventor： Michael Soulie ,  Thomas Martin

IPC: G06F15/78 ,  G06F1/08 ,  G06F1/14

CPC classification number: G06F15/7807 ,  G06F1/08 ,  G06F1/14

Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.

公开(公告)号：US11901901B2

公开(公告)日：2024-02-13

申请号：US18155232

申请日：2023-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkataratna Subrahmanya Bharathi Akondy Raja Raghupathi ,  Sam Gnana Sabapathy

IPC: H03K3/017 ,  G06F1/08 ,  H03K21/02

CPC classification number: H03K3/017 ,  G06F1/08 ,  H03K21/02

Abstract: In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

公开(公告)号：US11888487B2

公开(公告)日：2024-01-30

申请号：US18071794

申请日：2022-11-30

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Tsung-Han Tsai ,  Peng-Fei Lin ,  Kuo-Wei Chi

IPC: H03K5/135 ,  G06F1/08 ,  H03K5/131 ,  H03K5/00

CPC classification number: H03K5/135 ,  G06F1/08 ,  H03K5/131 ,  H03K2005/00058

Abstract: A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N−n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

公开(公告)号：US11882420B2

公开(公告)日：2024-01-23

申请号：US17431484

申请日：2020-01-22

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Nobuo Namekawa ,  Yutaka Takagi

IPC: H04R5/04 ,  G06F1/08 ,  G06F1/12 ,  G06F9/54 ,  H04R3/12

CPC classification number: H04R5/04 ,  G06F1/08 ,  G06F1/12 ,  G06F9/542 ,  H04R3/12

Abstract: An audio signal synchronization control device of the present disclosure includes a host controller, a plurality of audio devices, a communication unit capable of performing broadcast communication for controlling the plurality of audio devices from the host controller, and a clock oscillator that supplies a master clock of the same source oscillation to the plurality of audio devices. The host controller performs broadcast communication with a plurality of audio devices using a synchronization address. Each of the plurality of audio devices includes a synchronization control unit that generates a synchronization reset signal in a case where broadcast communication is performed by a synchronization address, a clock reset control unit that generates a timing signal in response to the synchronization reset signal, and an audio signal processing unit that processes audio data in accordance with the timing signal.

公开(公告)号：US20240019892A1

公开(公告)日：2024-01-18

申请号：US18452193

申请日：2023-08-18

Applicant: pSemi Corporation

Inventor： Gerald ALCORN

IPC: G06F1/08 ,  H03K19/17704 ,  G05B19/045

CPC classification number: G06F1/08 ,  H03K19/17716 ,  G05B19/045

Abstract: Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

公开(公告)号：US20240019890A1

公开(公告)日：2024-01-18

申请号：US18221226

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul MA ,  Daekyung KIM ,  Dongwook KIM ,  Byungki MOON ,  Sungbo PARK ,  Dongil SON ,  Hwayoung CHAE

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: According to an embodiment, an electronic device may include at least one communication processor comprising at least one central processing unit (CPU). According to an embodiment, the at least one communication processor may be configured to enter an RRC_Connected state. According to an embodiment, the at least one communication processor may be configured to control a clock level for the at least one CPU to be a first CPU clock level corresponding to the RRC_Connected state. According to an embodiment, the at least one communication processor may be configured to identify workload information comprising at least one of utilization information of the at least one CPU and traffic information of at least one bus of the at least one communication processor. According to an embodiment, the at least one communication processor may be configured provide the workload information as an input to an artificial intelligence (AI) model, wherein the AI model is trained using training data comprising at least one of CPU utilization information and bus traffic information as input values and CPU clock levels as output values. According to an embodiment, the at least one communication processor may be configured to identify, based on the providing the workload information as the input to the AI model, a second CPU clock level as an output of the AI model. Various other embodiments may be possible.

公开(公告)号：US11874792B2

公开(公告)日：2024-01-16

申请号：US17968646

申请日：2022-10-18

Applicant: GOWIN Semiconductor Corporation

Inventor： Grant Thomas Jennings

IPC: G06F13/42 ,  G06F1/08 ,  H03K19/17736 ,  H03M9/00 ,  H03M5/04

CPC classification number: G06F13/4291 ,  G06F1/08 ,  H03K19/17744 ,  H03M5/04 ,  H03M9/00 ,  G06F2213/0042

Abstract: A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.