公开(公告)号：US20100042871A1

公开(公告)日：2010-02-18

申请号：US12467733

申请日：2009-05-18

Applicant: Wilhard von Wendorff ,  Detlev Leisengang

Inventor： Wilhard von Wendorff ,  Detlev Leisengang

IPC: G06F11/20 ,  G06F15/80 ,  G06F9/06 ,  G06F11/07

CPC classification number: G06F11/16 ,  G06F11/20 ,  G06F2201/845

Abstract: A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of data or signals between the functional units. At least one functional unit of the system is programmable and/or configurable such that it performs a particular function out of a number of different functions. The connection matrix is programmed and/or configured such that the functional units are connected with each other in a particular configuration out of a number of different configurations.

Abstract translation: 提供了一种用于处理具有多个功能单元的数据或信号的方法和系统，每个功能单元适于将一个或多个功能应用于数据或信号，并且经由用于交换的连接矩阵彼此连接 的功能单元之间的数据或信号。 系统的至少一个功能单元是可编程和/或可配置的，使得其执行多个不同功能的特定功能。 连接矩阵被编程和/或配置为使得功能单元在多个不同配置中的特定配置中彼此连接。

公开(公告)号：US20090177872A1

公开(公告)日：2009-07-09

申请号：US11974349

申请日：2007-10-12

Applicant: Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich

Inventor： Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich

IPC: G06F9/30

CPC classification number: G06F9/4812 ,  G06F11/1497 ,  G06F11/1629 ,  G06F2201/845 ,  G06F2209/481

Abstract: A method for generating a valid signal for an application program in a signal processing system having a plurality of execution units which operate in a performance mode, and in which while the application program is running, a user switches the signal processing system to a comparison mode in which the mode the signals delivered by the execution units are compared with one another to generate the valid signal.

Abstract translation: 一种用于在具有以演奏模式操作的多个执行单元的信号处理系统中生成用于应用程序的有效信号的方法，并且在应用程序运行的同时，用户将信号处理系统切换到比较模式 其中由执行单元传递的信号彼此进行比较以产生有效信号。

公开(公告)号：US20080270746A1

公开(公告)日：2008-10-30

申请号：US11666175

申请日：2005-10-25

Applicant: Bernd Mueller ,  Eberhard Boehl

Inventor： Bernd Mueller ,  Eberhard Boehl

IPC: G06F9/30

CPC classification number: G06F11/183 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/1679 ,  G06F11/1695 ,  G06F2201/845

Abstract: A method and a device for performing switchover operations and for comparing signals in a computer system having at least two processing units, a switchover device being provided, and switchover operations being carried out between at least two operating modes, a comparator being provided, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode. At least two analog signals of the processing units are compared in such a way that, as a function of these signals, a difference is formed.

Abstract translation: 一种用于执行切换操作并用于比较具有至少两个处理单元的计算机系统中的信号的方法和装置，提供了切换装置，以及在至少两个操作模式之间执行的切换操作，提供了比较器，以及 对应于比较模式的第一操作模式和对应于演奏模式的第二操作模式。 将处理单元的至少两个模拟信号以这样的方式进行比较：作为这些信号的函数，形成差。

公开(公告)号：US20080163035A1

公开(公告)日：2008-07-03

申请号：US11666406

申请日：2005-10-25

Applicant: Thomas Kottke

Inventor： Thomas Kottke

IPC: G06F9/318 ,  G06F11/08

CPC classification number: G06F11/1695 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/1641 ,  G06F2201/845

Abstract: A unit and method for distributing data from at least one data source in a system provided with at least two computer units, containing switching means which are used to switch between at least two operating modes of the system, wherein data distribution and/or selection of a data source is dependent upon the operating mode.

Abstract translation: 一种用于在具有至少两个计算机单元的系统中从至少一个数据源分发数据的单元和方法，所述计算机单元包含用于在系统的至少两个操作模式之间切换的切换装置，其中数据分配和/或选择 数据源取决于操作模式。

公开(公告)号：US20080052494A1

公开(公告)日：2008-02-28

申请号：US10577022

申请日：2004-08-07

Applicant: Reinhard Weiberle ,  Thomas Kottke ,  Andreas Steininger

Inventor： Reinhard Weiberle ,  Thomas Kottke ,  Andreas Steininger

IPC: G06F15/76

CPC classification number: G06F9/30181 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/3885 ,  G06F11/1641 ,  G06F2201/845

Abstract: A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a first operating mode and a second operating mode. In the first operating mode, both execution units are supplied with the same operands, and in the second operating mode different operands are supplied to both execution units, and both execution units are controlled by the same control signals for the processing of the operands in the first operating mode, and both execution units are controlled by different control signals for the processing of the operands in the second operating mode.

Abstract translation: 一种用于具有至少两个执行单元的处理单元中的操作数处理的方法和装置，其能够以可预定的时钟周期操作。 执行单元由用于处理操作数的控制信号控制，并且可以在第一操作模式和第二操作模式之间切换。 在第一操作模式中，两个执行单元被提供相同的操作数，并且在第二操作模式中，将不同的操作数提供给两个执行单元，并且两个执行单元由相同的控制信号控制，用于处理 第一操作模式，并且两个执行单元由不同的控制信号控制，用于处理第二操作模式中的操作数。

公开(公告)号：US07249358B2

公开(公告)日：2007-07-24

申请号：US10248303

申请日：2003-01-07

Applicant: Philip G Emma ,  Allen P Haar ,  Paul D Kartschoke ,  Barry W Krumm ,  Norman J Rohrer ,  Peter A Sandon

Inventor： Philip G Emma ,  Allen P Haar ,  Paul D Kartschoke ,  Barry W Krumm ,  Norman J Rohrer ,  Peter A Sandon

IPC: G06F9/46 ,  G06F9/30 ,  G06F11/00

CPC classification number: G06F9/5044 ,  G06F9/30181 ,  G06F9/3885 ,  G06F11/1497 ,  G06F11/1637 ,  G06F11/182 ,  G06F11/184 ,  G06F2201/845

Abstract: A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Abstract translation: 一种具有多个处理器的计算机系统，其中每个处理器基于性能或可靠性被动态分配用于执行任务。

公开(公告)号：US20050240793A1

公开(公告)日：2005-10-27

申请号：US10819241

申请日：2004-04-06

Applicant: Kevin Safford ,  Donald Soltis

Inventor： Kevin Safford ,  Donald Soltis

IPC: G06F9/30 ,  G06F11/00

CPC classification number: G06F9/30181 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3851 ,  G06F11/1629 ,  G06F2201/845

Abstract: In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group without in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.

Abstract translation: 在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组， 可靠的运行模式。 电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则在不处于非高可靠性操作模式的情况下执行第一指令组。

公开(公告)号：US06772368B2

公开(公告)日：2004-08-03

申请号：US09734117

申请日：2000-12-11

Applicant: Sang Hoo Dhong ,  Harm Peter Hofstee ,  Ravi Nair ,  Steven Douglas Posluszny

Inventor： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Ravi Nair ,  Steven Douglas Posluszny

IPC: G06F1116

CPC classification number: G06F11/1641 ,  G06F9/30189 ,  G06F9/3861 ,  G06F9/3885 ,  G06F11/1407 ,  G06F2201/845

Abstract: In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic. The compare unit signals the commit logic in each respective processor that the possibility has been eliminated of a calculation interrupt arising for that instruction, once the compare unit receives signatures for corresponding versions of a result, but only if the signatures match. This permits the commit logic to commit the result. If the signatures do not match, the compare unit signals the commit logic that the corresponding instruction has faulted. The commit logic permits instructions prior to the faulting instruction in program order to continue execution, but initiates flushing of results that were produced by the faulting instruction and at least some instructions subsequent in program order to the faulting instruction.

Abstract translation: 在一个实施例中，多处理装置包括第一处理器和第二处理器。 每个处理器都有自己的数据和指令高速缓存来支持独立操作。 在正常模式下，处理器独立地执行单独的指令流。 每个处理器具有相应的签名生成器。 该系统还包括耦合到签名生成器的比较单元。 在高可靠性模式下，两个处理器执行相同的指令流。 也就是说，每个处理器计算流中的指令的结果的版本。 响应于各自的版本，相应的签名生成器向比较单元提供签名，从而可以检测到故障指令。 在另一方面，每个处理器具有其各自的提交逻辑。 一旦比较单元接收到相应版本的结果的签名，但只有当签名匹配时，比较单元才会发信号通知每个相应处理器中的提交逻辑已经消除了该指令产生的计算中断的可能性。 这允许提交逻辑提交结果。 如果签名不匹配，则比较单元向提交逻辑发出相应指令发生故障的信号。 提交逻辑允许以程序顺序执行故障指令之前的指令继续执行，但是启动由故障指令产生的结果和程序顺序中的至少一些指令冲洗到故障指令。

公开(公告)号：US20040123201A1

公开(公告)日：2004-06-24

申请号：US10324957

申请日：2002-12-19

Inventor： Hang T. Nguyen ,  Steven J. Tu ,  Alexander J. Honcharik ,  Sujat Jamil

IPC: G01R031/28 ,  G06F011/00

CPC classification number: G06F11/1641 ,  G06F11/1654 ,  G06F2201/845

Abstract: A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.

Abstract translation: 处理器包括以冗余（FRC）模式操作的第一和第二执行核心，用于比较来自第一和第二执行核心的结果的FRC检查单元和用于检测第一和第二核心中的可恢复错误的错误检查单元。 响应于检测到可恢复的错误，错误检测器禁用FRC检查器。 处理器的多模式实施例除了FRC模式之外还实现多核模式。 仲裁单元以多核心模式来管理由第一和第二执行核共享的资源的访问。 在多模式实施例中，FRC检验器位于仲裁单元附近。

公开(公告)号：US20030182492A1

公开(公告)日：2003-09-25

申请号：US10389443

申请日：2003-03-14

Applicant: Sun Microsystems, Inc.

Inventor： John E. Watkins ,  Paul J. Garnett ,  Stephen Rowlinson

IPC: G11C005/00

CPC classification number: G06F9/4812 ,  G06F11/1641 ,  G06F13/24 ,  G06F2201/845

Abstract: A computing system comprises two or more processing sets, for example for fault tolerant operation. The multiple processing sets have a connection to at least one device, typically many devices. The ownership of each device is allocated to one of the two or more processing sets. When an interrupt is generated within a device, this is transmitted from the device to the processing set to which ownership of the device has been allocated, but not to the remaining processing sets. In addition, a command for a device may be generated by a processing set. However, receipt of this command by the device is disabled if the processing set that generated the command has not been allocated ownership of the device.

Abstract translation: 计算系统包括两个或多个处理集合，例如用于容错操作。 多个处理集合具有至少一个设备的连接，通常是许多设备。 每个设备的所有权分配给两个或多个处理集中的一个。 当在设备内产生中断时，将从设备传输到已经分配设备所有权的处理集，而不是剩余的处理集。 此外，用于设备的命令可以由处理集合生成。 但是，如果生成命令的处理集尚未分配设备的所有权，则设备接收到该命令将被禁用。