公开(公告)号：US12106103B2

公开(公告)日：2024-10-01

申请号：US17795780

申请日：2020-04-07

Applicant: OMRON CORPORATION

Inventor： Daisuke Yagi ,  Toru Murata ,  Atsushi Kamimura ,  Yasuo Muneta

IPC: G06F9/30 ,  G06F11/14 ,  G06F11/16

CPC classification number: G06F9/3004 ,  G06F11/1497 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/14 ,  G06F11/16

Abstract: An information processing device that executes an arithmetic process includes a first processing circuit and a second processing circuit. The first processing circuit executes the arithmetic process N times consecutively. The second processing circuit executes the arithmetic process N times consecutively. N is an integer of 2 or more. The first processing circuit and the second processing circuit continue to operate according to a match between at least one result among the results of the N arithmetic processes executed by the first processing circuit and at least one result among the results of the N arithmetic processes executed by the second processing circuit. As a result, it is possible to suppress an increase in cost required for hardware and to suppress a temporary stop due to a temporary failure.

公开(公告)号：US20240059301A1

公开(公告)日：2024-02-22

申请号：US18260718

申请日：2022-01-06

Applicant: RENAULT S.A.S ,  NISSAN MOTOR CO., LTD.

Inventor： Patrice BERTRAND ,  Eric PERRAUD

IPC: B60W50/023 ,  G06F11/14

CPC classification number: B60W50/023 ,  G06F11/1497 ,  G06F2201/805

Abstract: A computing device includes a first unit and a second unit. In response to receipt of a request corresponding to a computing function, the first unit may: determine an execution context; trigger a first execution of the function on the second unit, this delivering a first comparison parameter, a first temporal execution parameter being associated with the first comparison parameter; trigger a second execution of the function on the second unit, this delivering a second comparison parameter, a second temporal execution parameter being associated with the second comparison parameter; compare the first and second comparison parameters, a temporal comparison parameter being associated with the result of the comparison; and determine a computing status.

公开(公告)号：US20230161675A1

公开(公告)日：2023-05-25

申请号：US18151543

申请日：2023-01-09

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  Prithvi Shankar YEYYADI ANANTHA

IPC: G06F11/14

CPC classification number: G06F11/1497 ,  G06F2201/87

Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

公开(公告)号：US20190079835A1

公开(公告)日：2019-03-14

申请号：US15822791

申请日：2017-11-27

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Chang Seok You ,  Min Su Kang ,  Sung Do Kim ,  Dong Hun Lee

IPC: G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1497 ,  G06F11/0739 ,  G06F11/0757

Abstract: An operating method of a vehicle watchdog circuit is provided. The method includes monitoring whether communication with a vehicle controller through a preset protocol is enabled and when a communication fault does not occur by monitoring whether communication is enabled, transmitting an error detection query to the vehicle controller every preset period. A response to the error detection query is received, and an operation of the vehicle controller is monitored, and upon determining that the operation of the vehicle controller is normal, a plurality of preset reset signals are sequentially transmitted to the vehicle controller.

公开(公告)号：US20180307574A1

公开(公告)日：2018-10-25

申请号：US15492757

申请日：2017-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tariq Hanif ,  Tin H. To

IPC: G06F11/273 ,  G06F11/22

CPC classification number: G06F11/3688 ,  G06F11/1497 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/187 ,  G06F11/2221 ,  G06F11/2294 ,  G06F11/3457 ,  G06F11/3684 ,  G06F11/3692

Abstract: Embodiments for automated testing of a virtualization management system are described. An example computer-implemented method for automated testing of a virtualization management system includes sending, by a test server, a test case to a plurality of instances of the system under test, the test case sent to each instance of the system under test via each interface from a plurality of interfaces supported by the system under test. The method further includes, for each instance of the system under test, performing multi-interface comparison. The comparison includes comparing, by the test server, responses to the test case from each of the interfaces. The method also includes in response to the responses from each of the interfaces being identical, storing the responses in an instance-response file corresponding to the instance. The method also includes reporting, by the test server, an error in response to the responses from each interface not being identical.

公开(公告)号：US09513903B2

公开(公告)日：2016-12-06

申请号：US14054643

申请日：2013-10-15

Applicant: Industrial Technology Research Institute

Inventor： Yung-Chang Chang ,  Hsing-Chuang Liu ,  Chih-Jen Yang

IPC: G06F11/16 ,  G06F9/30 ,  G06F11/18 ,  H03K19/003 ,  G06F11/14

CPC classification number: G06F9/3001 ,  G06F11/1497 ,  G06F11/1608 ,  G06F11/1629 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/183 ,  G06F11/188 ,  H03K19/0033

Abstract: A fault-tolerant system including a calculation unit and an output synthesizer is provided. The calculation unit receives a first environmental parameter and input data, wherein the calculation unit further includes a first and a second calculation circuits. The first calculation circuit is arranged to perform a calculation on the input data in response to the first environmental parameter to generate a first calculation result. The second calculation circuit is different from the first calculation circuit, and arranged to perform the calculation on the input data in response to the first environmental parameter to generate a second calculation result. The output synthesizer selects a first and a second set of bits from the first and the second calculation result according to a control signal, and synthesizes the first set of bits and the second set of bits in sequence to generate an adjusted calculation result.

Abstract translation: 提供了包括计算单元和输出合成器的容错系统。 计算单元接收第一环境参数和输入数据，其中所述计算单元还包括第一和第二计算电路。 第一计算电路被配置为响应于第一环境参数对输入数据进行计算以产生第一计算结果。 第二计算电路与第一计算电路不同，并且被配置为响应于第一环境参数对输入数据进行计算以产生第二计算结果。 输出合成器根据控制信号从第一和第二计算结果中选择第一组和第二组，并且顺序地合成第一组位和第二组位，以产生经调整的计算结果。

公开(公告)号：US20160188423A1

公开(公告)日：2016-06-30

申请号：US15073699

申请日：2016-03-18

Applicant: International Business Machines Corporation

Inventor： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

IPC: G06F11/14 ,  G11C7/10 ,  G11C29/52 ,  G06F11/16

CPC classification number: G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract translation: 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

公开(公告)号：US09329936B2

公开(公告)日：2016-05-03

申请号：US13732228

申请日：2012-12-31

Applicant: Intel Corporation

Inventor： Brian J. Hickman

IPC: G06F9/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/16

CPC classification number: G06F11/14 ,  G06F11/1497 ,  G06F11/1608 ,  G06F2201/845

Abstract: A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the reuse of underutilized hardware to implement spatial redundancy by using detection during the dispatch stage to determine if the operation may be executed by redundant hardware in the ALU. During execution, if determination is made that the correct conditions exists as determined by the redundant execution modes, the SuperFMA ALU performs the operation with redundant execution and compares the results for a match in order to generate a computational result. The method to increase computational reliability by using redundant execution is advantageous because the hardware cost of adding support for redundant execution is low and the complexity of implementation of the disclosed method is minimal due to the reuse of existing hardware.

Abstract translation: 一种通过使用SuperFMA ALU通过使用数据路径的不充分部分来增加计算可靠性的系统，处理器和方法。 该方法允许利用未充分利用的硬件来重新利用在调度阶段使用检测来实现空间冗余，以确定该操作是否可以由ALU中的冗余硬件执行。 在执行期间，如果确定冗余执行模式所确定的正确条件，SuperFMA ALU将执行冗余执行操作，并比较匹配结果以生成计算结果。 通过使用冗余执行来增加计算可靠性的方法是有利的，因为对冗余执行的添加支持的硬件成本低，并且由于现有硬件的重用而使所公开的方法的实施的复杂度最小。

公开(公告)号：US20150212905A1

公开(公告)日：2015-07-30

申请号：US14163345

申请日：2014-01-24

Applicant: International Business Machines Corporation

Inventor： Michael Karl Gschwind ,  Valentina Salapura

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/46

CPC classification number: G06F12/0875 ,  G06F9/467 ,  G06F11/0715 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0772 ,  G06F11/1415 ,  G06F11/1474 ,  G06F11/1492 ,  G06F11/1497 ,  G06F2201/83 ,  G06F2212/452 ,  H04L9/3242

Abstract: Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional executions is provided. Included is identifying a first indicator, by a computer system, signaling a beginning instruction of a transaction comprising a plurality of instructions; generating, by the computer system, a computed digest based on the execution of at least one of the plurality of instructions; accumulating, by the computer system, a diagnostic data of the transaction based on the execution of the plurality of instructions; identifying, by the computer system, a second indicator associated with the plurality of instructions signaling an ending instruction of the transaction comprising the plurality of instructions; and based on an abort of the transaction, not saving the memory store data of the transaction to memory.

公开(公告)号：US09075621B2

公开(公告)日：2015-07-07

申请号：US13336432

申请日：2011-12-23

Applicant: Guillaume Schon ,  Mélanie Emanuelle Lucie Teyssier ,  Frederic Claude Marie Piry ,  Luca Scalabrino ,  David Michael Bull

Inventor： Guillaume Schon ,  Mélanie Emanuelle Lucie Teyssier ,  Frederic Claude Marie Piry ,  Luca Scalabrino ,  David Michael Bull

IPC: G06F9/38 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F9/3865 ,  G06F9/3855 ,  G06F9/3861 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/1405 ,  G06F11/1497

Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.

Abstract translation: 数据处理装置以流水线执行阶段的顺序执行指令。 错误检测单元对与执行指令相关联的信号进行两次采样，并且如果样本不同则产生误差信号。 异常存储单元维护与发出到执行流水线的指令相对应的条目的年龄排序列表，并且可以标记条目以显示是否已经与该指令相关联地生成了错误信号。 定时器单元响应于产生误差信号以启动预定时间段的定时。 如果列表中的最旧的等待条目具有与其相关联地存储的所述错误标记，则错误恢复单元启动软管道冲洗过程，并且如果所述预定时间段过去则启动硬管道冲洗过程，所述硬冲洗程序包括将所述流水线重置为 预定状态。