公开(公告)号：US20040087166A1

公开(公告)日：2004-05-06

申请号：US10289807

申请日：2002-11-06

Inventor： Patrick Morrow

IPC: H01L021/311

CPC classification number: H01L21/76811 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/76813 ,  H01L21/76835 ,  H01L2221/1036

Abstract: An improved method of forming a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A first part of the second hard masking layer and a first part of the first hard masking layer are etched to form an etched region within the hard mask that exposes a first portion of the dielectric layer. That etched region is filled with a sacrificial material. After etching through a second part of the second hard masking layer, the remainder of the sacrificial material is removed prior to subsequent processing.

Abstract translation: 描述了一种形成半导体器件的改进方法。 最初，形成包括覆盖电介质层的第一和第二硬掩模层的结构。 蚀刻第二硬掩模层的第一部分和第一硬掩模层的第一部分以在硬掩模内形成暴露电介质层的第一部分的蚀刻区域。 该蚀刻区域填充有牺牲材料。 在蚀刻通过第二硬掩模层的第二部分之后，在随后的处理之前去除剩余的牺牲材料。

公开(公告)号：US20040000718A1

公开(公告)日：2004-01-01

申请号：US10608126

申请日：2003-06-30

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Nobuo Aoi

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L21/76835 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: An organic-inorganic hybrid film is deposited on a substrate by introducing, into a vacuum chamber, a gas mixture of a silicon alkoxide and an organic compound and generating a plasma derived from the gas mixture. Then, a hydrogen plasma process is performed with respect to the organic-inorganic hybrid film by introducing, into the vacuum chamber, a gas containing a reducing gas and generating a plasma derived from the gas. As a result, an organic component in the organic-inorganic hybrid film eliminates therefrom and numerous fine holes are formed in hollow portions from which the organic component has eliminated, whereby a porous film composed of the organic-inorganic hybrid film is obtained.

Abstract translation: 通过在真空室中引入硅醇盐和有机化合物的气体混合物并产生来自气体混合物的等离子体，将有机 - 无机杂化膜沉积在基板上。 然后，通过向真空室中引入含有还原气体的气体并产生来自气体的等离子体，对有机 - 无机杂化膜进行氢等离子体处理。 结果，有机 - 无机杂化膜中的有机成分消失，并且有机成分被除去的中空部分形成许多细孔，得到由有机 - 无机杂化膜构成的多孔膜。

公开(公告)号：US20030232498A1

公开(公告)日：2003-12-18

申请号：US10454680

申请日：2003-06-05

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Takeshi Harada

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76838 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2221/1036

Abstract: A recess is formed in an insulating film, and then a conductive film is deposited over the insulating film so as to fill the recess. Thereafter, a heat treatment is performed on the conductive film. Subsequently, the conductive film is partly removed both before and after the step of performing the heat treatment.

Abstract translation: 在绝缘膜中形成凹部，然后在绝缘膜上沉积导电膜以填充凹部。 之后，对导电膜进行热处理。 随后，在进行热处理的步骤之前和之后，部分地去除导电膜。

公开(公告)号：US06649495B2

公开(公告)日：2003-11-18

申请号：US10164709

申请日：2002-06-10

Applicant: Yoshimi Shioya ,  Yuhko Nishimoto ,  Tomomi Suzuki ,  Hiroshi Ikakura ,  Kazuo Maeda

Inventor： Yoshimi Shioya ,  Yuhko Nishimoto ,  Tomomi Suzuki ,  Hiroshi Ikakura ,  Kazuo Maeda

IPC: H01L2120

CPC classification number: H01L21/76834 ,  C23C16/0272 ,  C23C16/401 ,  C23C16/5096 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2221/1036

Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated. Its constitution includes the steps of: forming the barrier insulating film 35a on a substrate 21 subject to deposition, in which an electric power having a first frequency (f1) is applied to a first film forming gas containing at least silicon-containing gas and oxygen-containing gas to transform said first film forming gas into plasma and to cause reaction; and forming the main insulating film 35b having low relative dielectric constant on the barrier insulating film 35a, in which an electric power having a second frequency (f2) higher than the first frequency (f1) is applied to a second film forming gas containing at least the silicon-containing gas and the oxygen-containing gas to transform the second film forming gas into plasma and to cause reaction.

Abstract translation: 半导体器件的制造方法技术领域本发明涉及一种半导体器件的制造方法，其中，在主要由铜膜构成的布线被涂覆的同时依次形成具有低相对介电常数的阻挡绝缘膜和主绝缘膜。 其结构包括以下步骤：在沉积的基板21上形成阻挡绝缘膜35a，其中具有第一频率（f1）的电力施加到至少含有含硅气体和氧气的第一成膜气体 以将所述第一成膜气体转化为等离子体并引起反应; 并且在隔离绝缘膜35a上形成具有低相对介电常数的主绝缘膜35b，其中具有比第一频率（f1）高的第二频率（f2）的电力施加到至少包含至少 含硅气体和含氧气体，以将第二成膜气体转化为等离子体并引起反应。

公开(公告)号：US06645873B2

公开(公告)日：2003-11-11

申请号：US09881255

申请日：2001-06-14

Applicant: Akira Shimizu ,  Fumitoshi Ozaki

Inventor： Akira Shimizu ,  Fumitoshi Ozaki

IPC: H01L21302

CPC classification number: H01L21/76807 ,  H01L21/31116 ,  H01L21/31629 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of processing a semiconductor substrate involves etching a SiOF layer with HF or HF+H2O. The method can be used to form hollow structures in semiconductor substrates and thus provides a way to make interlayer insulators.

公开(公告)号：US20030022468A1

公开(公告)日：2003-01-30

申请号：US10164709

申请日：2002-06-10

Inventor： Yoshimi Shioya ,  Yuhko Nishimoto ,  Tomomi Suzuki ,  Hiroshi Ikakura ,  Kazuo Maeda

IPC: H01L021/20

CPC classification number: H01L21/76834 ,  C23C16/0272 ,  C23C16/401 ,  C23C16/5096 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2221/1036

Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated. Its constitution includes the steps of: forming the barrier insulating film 35a on a substrate 21 subject to deposition, in which an electric power having a first frequency (f1) is applied to a first film forming gas containing at least silicon-containing gas and oxygen-containing gas to transform said first film forming gas into plasma and to cause reaction; and forming the main insulating film 35b having low relative dielectric constant on the barrier insulating film 35a, in which an electric power having a second frequency (f2) higher than the first frequency (f1) is applied to a second film forming gas containing at least the silicon-containing gas and the oxygen-containing gas to transform the second film forming gas into plasma and to cause reaction.

公开(公告)号：US06417087B1

公开(公告)日：2002-07-09

申请号：US09465075

申请日：1999-12-16

Applicant: Sailesh Chittipeddi ,  William Thomas Cochran ,  Yehuda Smooha

Inventor： Sailesh Chittipeddi ,  William Thomas Cochran ,  Yehuda Smooha

IPC: H01L2144

CPC classification number: H01L24/48 ,  H01L21/76807 ,  H01L23/53209 ,  H01L24/05 ,  H01L24/11 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Abstract translation: 用于在集成电路内形成双镶嵌键合焊盘的工艺产生接合焊盘，其抵抗应力作用并因此允许在有源电路上形成接合焊盘。 该方法包括通过在开口的上部的底部表面上形成具有阻挡层膜的接合焊盘开口形成双镶嵌结构，以及形成向下延伸通过底表面的通孔。 该工艺产生接合焊盘，其抵抗诸如当将外部电线接合到接合焊盘时可产生的应力作用的破坏。 防止接合焊盘和底层电路之间的泄漏电流。

公开(公告)号：US20020076921A1

公开(公告)日：2002-06-20

申请号：US09998649

申请日：2001-12-03

Inventor： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

IPC: H01L021/4763

CPC classification number: H01L21/76874 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

公开(公告)号：US20010053592A1

公开(公告)日：2001-12-20

申请号：US09876207

申请日：2001-06-06

Applicant: NEC Corporation

Inventor： Shuji Sone

IPC: H01L021/20

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76859 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1null1017 cmnull2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400null C.

Abstract translation: 在扩散层上形成层间绝缘膜和连接到MOS晶体管中的扩散层的第一通孔。 然后，形成用于第一层铜互连的低介电常数膜和连接到第一通孔的第一层铜互连。 然后，依次形成蚀刻停止膜，层间绝缘膜和用于第二层铜互连的低介电常数膜。 然后，在蚀刻停止膜和层间绝缘膜中形成通孔，并且在用于第二层铜互连的低介电常数膜中形成沟槽。 然后形成阻挡金属层。 此后，植入Ar离子。 此时，注入能量为50keV，剂量为1×10 17 cm -2。 形成第二通孔和第二层铜互连，并在400℃的温度下进行退火。

公开(公告)号：US06261949B1

公开(公告)日：2001-07-17

申请号：US09286704

申请日：1999-04-06

Applicant: Mitsunari Sukekawa

Inventor： Mitsunari Sukekawa

IPC: H01L214763

CPC classification number: H01L21/76808 ,  H01L2221/1031 ,  H01L2221/1036

Abstract: A contact hole is formed in the first interlayer insulation film on a semiconductor substrate. While making the contact hole remaining a cavity, the second interlayer insulation film is formed on the first interlayer insulation film. Thereafter, a resist film having a wiring groove pattern is formed on the second interlayer insulation film. Using this resist film as a mask, the second interlayer insulation film is etched. By so doing, a wiring groove is formed in the second interlayer insulation film, and the contact hole which remains a cavity is opened, thereby forming a wiring groove and a contact hole substantially simultaneously. A nitride film formed between the first interlayer insulation film and the second interlayer insulation film may, therefore, merely function as an etching stopper. Thus, it is possible to either make the nitride film thinner than the conventional nitride film or to dispense with the nitride film. Hence, it is possible to reduce the capacity of the interlayer wiring.

Abstract translation: 在半导体衬底上的第一层间绝缘膜中形成接触孔。 在使接触孔保持空腔的同时，在第一层间绝缘膜上形成第二层间绝缘膜。 此后，在第二层间绝缘膜上形成具有布线槽图案的抗蚀剂膜。 使用该抗蚀剂膜作为掩模，蚀刻第二层间绝缘膜。 通过这样做，在第二层间绝缘膜中形成布线槽，并且保持空腔的接触孔被打开，从而基本上同时形成布线槽和接触孔。 因此，形成在第一层间绝缘膜和第二层间绝缘膜之间的氮化物膜可以仅用作蚀刻停止层。 因此，可以使氮化物膜比常规的氮化物膜更薄或者省去氮化物膜。 因此，可以降低层间布线的容量。