公开(公告)号：US06576081B2

公开(公告)日：2003-06-10

申请号：US09438665

申请日：1999-11-12

Applicant: Hiroaki Date ,  Yuko Motoyama ,  Hideshi Tokuhira ,  Makoto Usui ,  Nobuhiro Imaizumi

Inventor： Hiroaki Date ,  Yuko Motoyama ,  Hideshi Tokuhira ,  Makoto Usui ,  Nobuhiro Imaizumi

IPC: C09J902

CPC classification number: H01L24/28 ,  H01L21/563 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29373 ,  H01L2224/29386 ,  H01L2224/2949 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83097 ,  H01L2224/83099 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/303 ,  H05K3/386 ,  Y10T156/1011 ,  Y10T156/1018 ,  Y10T156/1026 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present invention is characterized by comprising a two-pack adhesive of an A agent selected from components, an acrylic monomer, a peroxide, a reducing agent, an epoxy resin precursor and a curing agent and containing at least one or two of the acrylic monomer, the peroxide and the reducing agent, and a B agent containing all of the remaining components which are not selected in the A agent. The use of this adhesive makes it possible to stably obtain the bonding free from a thermal stress with the excellent heat resistance and the good reliability.

Abstract translation: 本发明的特征在于包括选自组分，丙烯酸类单体，过氧化物，还原剂，环氧树脂前体和固化剂的A试剂的双组分粘合剂，并且含有至少一种或两种丙烯酸类单体 ，过氧化物和还原剂，以及含有在A剂中未选择的所有剩余成分的B剂。 通过使用这种粘合剂，可以稳定地获得没有热应力的结合，具有优异的耐热性和良好的可靠性。

公开(公告)号：US12046573B2

公开(公告)日：2024-07-23

申请号：US17697708

申请日：2022-03-17

Applicant: SK hynix Inc.

Inventor： Jin Woong Kim ,  Mi Seon Lee

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/30 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2746 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3015 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30517 ,  H01L2224/30519 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/81201 ,  H01L2224/83048 ,  H01L2224/83201 ,  H01L2924/04941 ,  H01L2924/05042

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

公开(公告)号：US12040208B2

公开(公告)日：2024-07-16

申请号：US17540859

申请日：2021-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghee Kim ,  Seungran Park ,  Youngki Jung ,  Chulgyu Jung

IPC: H01L21/68 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L21/68 ,  H01L24/95 ,  H01L25/167 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/80085 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/83085 ,  H01L2224/83136 ,  H01L2224/83201 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95136 ,  H01L2924/12041

Abstract: A guide apparatus configured to transfer light-emitting devices in a liquid onto a substrate is provided. The guide apparatus includes a base configured to support the substrate; and a guide member configured to couple with the base to be seated on a mounting surface of the substrate in a state in which the substrate is supported on a surface of the base, wherein the guide member includes guide holes configured to respectively guide the light-emitting devices in the liquid to be disposed on the mounting surface of the substrate.

公开(公告)号：US20240203754A1

公开(公告)日：2024-06-20

申请号：US18527731

申请日：2023-12-04

Applicant: Arieca Inc.

Inventor： Navid Kazem ,  Dylan S. Shah ,  Jeffrey Gelorme ,  Hing Jii Mea ,  Keyton D. Feller

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L21/4882 ,  H01L23/3733 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29005 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29301 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29347 ,  H01L2224/2936 ,  H01L2224/29366 ,  H01L2224/29372 ,  H01L2224/29379 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/2939 ,  H01L2224/3201 ,  H01L2224/32221 ,  H01L2224/83201 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2924/0108 ,  H01L2924/0133 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/0695 ,  H01L2924/07001 ,  H01L2924/0715 ,  H01L2924/095

Abstract: A method of deposition of a thermal interface material onto a circuit assembly and an integrated circuit formed therefrom is provided. The method includes depositing a thermal interface material at a first layer thickness between a first layer of a circuit assembly and a second layer of the circuit assembly. The thermal interface material includes an emulsion of liquid metal droplets and polymer. The first layer thickness is at least 1.1 times a D90 of the liquid metal droplets prior to compressing the circuit assembly. The method includes compressing the circuit assembly to decrease the first layer thickness to a second layer thickness, thereby deforming the liquid metal droplets. The second layer thickness is no greater than a D90 of the liquid metal droplets in thermal interface material prior to compressing the circuit assembly.

公开(公告)号：US20240178126A1

公开(公告)日：2024-05-30

申请号：US18549447

申请日：2022-03-14

Applicant: VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.

Inventor： Guo-Quan LU ,  Zichen ZHANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49866 ,  H01L23/3735 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L25/072 ,  H01L21/4853 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83201 ,  H01L2224/8384 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/20106

Abstract: Multi-chip module packaging technologies for GaN and other devices are described. The power module packaging technology described can be applied to all types of medium-voltage devices, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or the latest gallium oxide (Ga2O3) devices. In one example, a power module includes a first substrate, a second substrate, a sintered-silver semiconductor die pillar, the pillar being positioned between the first substrate and the second substrate, a terminal on a first side of the power module, and a terminal on a second side of the power module.

公开(公告)号：US20240145421A1

公开(公告)日：2024-05-02

申请号：US18384396

申请日：2023-10-27

Applicant: SOLAR APPLIED MATERIALS TECHNOLOGY CORP.

Inventor： Kuan-Neng CHEN ,  Zhong-Jie HONG ,  Chih-I CHO ,  Ming-Wei WENG ,  Chih-Han CHEN ,  Chiao-Yen WANG ,  Ying-Chan HUNG ,  Hong-Yi WU ,  CHENG-YEN HSIEH

IPC: H01L23/00 ,  C23C14/18

CPC classification number: H01L24/29 ,  C23C14/185 ,  H01L24/83 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29157 ,  H01L2224/29176 ,  H01L2224/29624 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29647 ,  H01L2224/29664 ,  H01L2224/29669 ,  H01L2224/29676 ,  H01L2224/8302 ,  H01L2224/83201

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

公开(公告)号：US20240071898A1

公开(公告)日：2024-02-29

申请号：US18343232

申请日：2023-06-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Koji OSAKI ,  Yuichiro HINATA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L29/16

CPC classification number: H01L23/49861 ,  H01L21/4825 ,  H01L23/49844 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/18 ,  H01L29/1608 ,  H01L2224/32225 ,  H01L2224/4846 ,  H01L2224/73265 ,  H01L2224/83201 ,  H01L2224/83885 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device includes a semiconductor chip having a main electrode on a front surface thereof, a wiring board having a front surface to which a rear surface of the semiconductor chip is bonded, a sealing member sealing the wiring board and the semiconductor chip, and an adhesive layer including at least two adhesive films that are laminated to each other. The adhesive layer is provided on surfaces of the wiring board and the semiconductor chip so that the sealing member seals the wiring board and the semiconductor chip via the adhesive layer. As a result, the sealing member is able to reliably seal the semiconductor chip and wiring board via the adhesive layer, thereby preventing an occurrence and extension of separation.

公开(公告)号：US20240055422A1

公开(公告)日：2024-02-15

申请号：US18344314

申请日：2023-06-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tatsuo NISHIZAWA

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/83 ,  H01L2224/8384 ,  H01L2224/83201 ,  H01L2224/32245 ,  H01L24/32 ,  H01L2224/48175 ,  H01L24/48 ,  H01L2224/73265 ,  H01L24/73

Abstract: A method for manufacturing a semiconductor module includes arranging an insulating wiring board on a lower die, arranging sintered materials at a plurality of points on the insulating wiring board, arranging each semiconductor chip on the sintered materials, arranging each buffer material individually on the semiconductor chips, arranging, above the lower die, an upper die including protrusions at points corresponding to arrangement positions of the semiconductor chips so that the protrusions correspond to the semiconductor chips, and sintering by pressurizing and heating the sintered materials by the protrusions through the buffer materials and the semiconductor chips.

公开(公告)号：US20240038749A1

公开(公告)日：2024-02-01

申请号：US18379682

申请日：2023-10-13

Applicant: InnoLux Corporation

Inventor： Yuan-Lin Wu ,  Kuan-Feng Lee ,  Tsung-Han Tsai ,  Jia-Yuan Chen

IPC: H01L25/16 ,  H01L27/12 ,  H01L33/54 ,  H01L33/62 ,  H01L33/48 ,  H01L33/46 ,  H01L33/50 ,  H01L23/00 ,  H01L25/075 ,  H01L23/538

CPC classification number: H01L25/167 ,  H01L27/1218 ,  H01L33/54 ,  H01L33/62 ,  H01L33/48 ,  H01L33/46 ,  H01L33/505 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0753 ,  H01L23/5387 ,  H01L2224/83201 ,  H01L33/06

Abstract: A display device having a display region includes a substrate, a plurality of organic light emitting parts disposed on the substrate in the display region, an organic layer disposed on at least one of the plurality of organic light emitting parts, a circuit layer disposed on the substrate, and a first layer disposed between the organic layer and the circuit layer. At least a portion of the organic layer has a curved profile.

公开(公告)号：US20230411334A1

公开(公告)日：2023-12-21

申请号：US17865586

申请日：2022-07-15

Applicant: BOARDTEK ELECTRONICS CORPORATION

Inventor： CHIEN-CHENG LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L24/20 ,  H01L24/32 ,  H01L24/19 ,  H01L23/49827 ,  H01L23/367 ,  H01L21/486 ,  H01L21/4867 ,  H01L24/29 ,  H01L2224/29339 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/19 ,  H01L2224/211

Abstract: A high-frequency power module less vulnerable to parasitic phenomena includes first base board, power chip, and second base board. The first base board includes a first substrate, a first conductive wiring layer, and a second conductive wiring layer on each side of the first substrate. The power chip is disposed on the first conductive wiring layer. The second base board includes a second substrate covering the power chip and the first conductive wiring layer, and a third conductive wiring layer away from the first conductive wiring layer. First conductive structures penetrate the second substrate to connect the third conductive wiring layer with the power chip, greatly reducing the lengths of signal paths between components and so parasitic effects A second conductive structure penetrates the first and second substrates to connect the first, second, and third conductive wiring layers. A manufacturing method is also disclosed.