公开(公告)号：US20240332241A1

公开(公告)日：2024-10-03

申请号：US18744174

申请日：2024-06-14

Applicant: SK hynix Inc.

Inventor： Jin Woong KIM ,  Mi Seon LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/30 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2746 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3015 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30517 ,  H01L2224/30519 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/81201 ,  H01L2224/83048 ,  H01L2224/83201 ,  H01L2924/04941 ,  H01L2924/05042

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

公开(公告)号：US20240312860A1

公开(公告)日：2024-09-19

申请号：US18467581

申请日：2023-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Daisuke KOIKE ,  Hisashi TOMITA ,  Yuning TSAI ,  Yutaro HAYASHI

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L29/739

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/7393 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/83201 ,  H01L2224/8348

Abstract: A semiconductor device according to an embodiment includes: a semiconductor chip; a conductive sheet provided on the semiconductor chip; and a metal plate provided on the conductive sheet. The metal plate has a step portion that is provided on a lateral surface, or a groove portion that is provided on a bottom surface.

公开(公告)号：US20240304596A1

公开(公告)日：2024-09-12

申请号：US18179072

申请日：2023-03-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Dukyong LEE ,  Hao YAN ,  Kun FENG

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/27003 ,  H01L2224/2711 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27438 ,  H01L2224/277 ,  H01L2224/27848 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83201 ,  H01L2224/8384

Abstract: Implementations of a sintering film frame may include a frame including an outer perimeter and an inner perimeter, the inner perimeter defining an opening through the frame; a position detection opening through the frame; at least two alignment holes through the frame; and a frame identifier on a side of the frame.

公开(公告)号：US20240258262A1

公开(公告)日：2024-08-01

申请号：US18426144

申请日：2024-01-29

Applicant: THE INDIUM CORPORATION OF AMERICA

Inventor： Milos Lazic ,  Richard McDonough

IPC: H01L23/00 ,  H01L23/367

CPC classification number: H01L24/26 ,  H01L23/367 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2732 ,  H01L2224/29105 ,  H01L2224/3207 ,  H01L2224/32221 ,  H01L2224/83201 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105

Abstract: Described are a double barrier system and method used to contain a thermal interface material to avoid unwanted interactions of the thermal interface material with other metals or components within a semiconductor device. In one implementation, a semiconductor assembly includes: a substrate; a heat generating device including a first surface attached to the substrate; a first barrier surrounding and in touching relation with the heat generating device; a second barrier surrounding the first barrier such that there is an area between the first barrier and the second barrier; a heat transferring device; and a thermal interface material between and in touching relation with the heat transferring device and a second surface of the heat generating device opposite the first surface.

公开(公告)号：US20240128227A1

公开(公告)日：2024-04-18

申请号：US18486467

申请日：2023-10-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Perceval COUDRAIN ,  Arnaud GARNIER ,  Jeanne PIGNOL

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/427 ,  H01L23/552

CPC classification number: H01L24/32 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/427 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L24/96 ,  H01L21/568 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/27845 ,  H01L2224/29082 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29166 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/83005 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83895 ,  H01L2224/83948 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109

Abstract: A SiP-type electronic device, including an electronic chip provided with an electrical interconnection face; a redistribution layer electrically coupled to the electrical interconnection face of the chip; electrical connection elements electrically coupled to the chip by the redistribution layer which is arranged between the chip and the connection elements; a first metal layer arranged on the side of a second face of the chip and secured to this second face; an encapsulation material arranged around the chip, between the redistribution layer and the first metal layer; a second metal layer including a first face secured by direct bonding to the first metal layer; a substrate arranged against a second face of the second metal layer.

公开(公告)号：US11908829B2

公开(公告)日：2024-02-20

申请号：US17350856

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/83 ,  H01L23/5283 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/2784 ,  H01L2224/27452 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83201 ,  H01L2924/37001

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

公开(公告)号：US20240030176A1

公开(公告)日：2024-01-25

申请号：US18112323

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Yong PARK ,  Jeong Hyun Lee ,  Choon Bin Yim

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13

CPC classification number: H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L21/565 ,  H01L21/561 ,  H01L21/4853 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/13 ,  H01L24/83 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/3201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1011 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/29005 ,  H01L2224/83091 ,  H01L2224/83201

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.

公开(公告)号：US20230215838A1

公开(公告)日：2023-07-06

申请号：US17928318

申请日：2021-05-19

Applicant: Siemens Aktiengesellschaft

Inventor： Bernd Müller ,  Christian Nachtigall-Schellenberg ,  Jörg Strogies ,  Klaus Wilke

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/92 ,  H01L24/33 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L21/563 ,  H01L23/3185 ,  H01L2224/33183 ,  H01L2224/3303 ,  H01L2224/29191 ,  H01L2924/0715 ,  H01L2224/29291 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/9211 ,  H01L2224/81201 ,  H01L2224/83201 ,  H01L2224/8184 ,  H01L2224/83102 ,  H01L23/585

Abstract: Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

公开(公告)号：US20230207517A1

公开(公告)日：2023-06-29

申请号：US17975462

申请日：2022-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tsunehiro NAKAJIMA

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/97 ,  H01L2224/83022 ,  H01L2224/8384 ,  H01L2224/83201 ,  H01L2224/83048 ,  H01L2224/83026 ,  H01L2224/97 ,  H01L2224/29199 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L24/29

Abstract: A semiconductor device manufacturing method, including: a first treatment process for reducing an amount of oxygen and carbon adsorbed to a main surface of the conductive plate to 20 atomic % or less; a first checking process for checking whether the conductive plate has a temperature no higher than a reference temperature; a chip placement process for placing, responsive to the conductive plate having the temperature no higher than the reference temperature, a semiconductor chip on the main surface of the conductive plate via a sinter material; a first bonding process for applying heat and pressure to the sinter material according to a first condition that allows the organic substance to partially remain; a preparatory process for making preparations for further bonding the semiconductor chip; and a second bonding process for further applying heat and pressure to the sinter material according to a second condition that sinters the sinter material.

公开(公告)号：US20190115313A1

公开(公告)日：2019-04-18

申请号：US16229585

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： ALEXANDER KALNITSKY ,  YI-YANG LEI ,  HSI-CHING WANG ,  CHENG-YU KUO ,  TSUNG LUNG HUANG ,  CHING-HUA HSIEH ,  CHUNG-SHI LIU ,  CHEN-HUA YU ,  CHIN-YU KU ,  DE-DUI LIAO ,  KUO-CHIO LIU ,  KAI-DI WU ,  KUO-PIN CHANG ,  SHENG-PIN YANG ,  ISAAC HUANG

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L24/83 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/03 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/921 ,  H01L2224/94 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.