Protocol for asynchronous character communication
    42.
    发明授权
    Protocol for asynchronous character communication 失效
    异步字符通信协议

    公开(公告)号:US5452302A

    公开(公告)日:1995-09-19

    申请号:US914186

    申请日:1992-07-15

    Inventor: Ronald C. Lewis

    CPC classification number: H04L1/0078 H04L29/06 H04L7/10

    Abstract: A first module (10) sends a message comprising a plurality of data characters to a second module (20) provided, however, that upon sending an individual data character, the first module waits to receive an acknowledgement character from the second module before proceeding to send another data character.

    Abstract translation: 然而,第一模块(10)向包括第二模块(20)的第二模块(20)发送包括多个数据字符的消息,然而,在发送单个数据字符之后,第一模块等待从第二模块接收确认字符,然后继续 发送另一个数据字符。

    Computer networking method
    43.
    发明授权
    Computer networking method 失效
    计算机联网方式

    公开(公告)号:US5191585A

    公开(公告)日:1993-03-02

    申请号:US318124

    申请日:1989-03-02

    CPC classification number: H04L29/06 H04L1/0078

    Abstract: A computer networking method is disclosed, including methods of building packets of information, transmitting packets of information, and processing information received from another device in a network, wherein when data packets are built, they are initially built only with an address appended to the data in the packet but once a threshold level of failed transmission is encountered, a second type of information packet is built having error correcting means built therein.

    Abstract translation: 公开了一种计算机联网方法,包括构建信息包,传送信息包和处理从网络中的另一设备接收的信息的方法,其中当构建数据分组时,它们最初仅以附加到数据的地址构建 在分组中,但是一旦遇到失败的传输的阈值级别,则构建其中内置错误校正装置的第二类型的信息分组。

    Telephone or data switching system with variable protocol inter-office
communication
    44.
    发明授权
    Telephone or data switching system with variable protocol inter-office communication 失效
    具有可变协议的办公室间通信的电话或数据交换系统

    公开(公告)号:US5140590A

    公开(公告)日:1992-08-18

    申请号:US494668

    申请日:1990-03-16

    Abstract: A method of producing interoffice signalling comprising storing program blocks for commanding generation, in a plurality of signalling protocols, of signalling signals in a communication switching system, storing correlations of particular ones of the program blocks with a particular protocol for signalling functions related to the process of a call to or from the communication switching system, enabling operation of the particular ones of the program blocks when a particular signalling signal is to be generated in the processing of a telephone call to or from the communication switching system, to match the particular protocol, whereby the communication switching system is enable to process calls restricted to the particular protocol out of the plurality of protocols for a particular call.

    Abstract translation: 一种产生区间信令的方法,包括存储用于在多个信令协议中在通信交换系统中命令生成信令信号的程序块,存储特定程序块的特定协议与用于与该过程相关的信令功能的特定协议的相关性 来自或来自通信交换系统的呼叫,当在处理来自或来自通信交换系统的电话呼叫中产生特定信令信号时,使能特定方案块的操作,以匹配特定协议 ,由此通信交换系统能够处理针对特定呼叫的多个协议中限定于特定协议的呼叫。

    Method of transmitting binary information using 3 signals per time slot
    45.
    发明授权
    Method of transmitting binary information using 3 signals per time slot 失效
    每个时隙使用3个信号发送二进制信息的方法

    公开(公告)号:US4253185A

    公开(公告)日:1981-02-24

    申请号:US57179

    申请日:1979-07-13

    Inventor: Daniel Danielsen

    CPC classification number: H04L25/4925 H04L1/0078 H04L25/4919

    Abstract: A self-synchronizing transmission loop consists of a transceiver, a transponder, a data link for transmitting a group of eight binary numbers from the transceiver to the transponder, and a data link for transmitting a group of eight binary numbers from the transponder to the transceiver. Each of the transceiver and the transponder uses a bipolar return-to-zero direct-current signal format where each binary number to be transmitted has its own transmission time slot divided into three substantially equal successive time segments T1, T2 and T3. Time segment T1 provides a change from zero level to a single unit level signal of positive polarity (+1) for binary 1 and of negative polarity (-1) for binary 0, time segment T2 provides a reversal of the single unit level signal of time segment T1, and time segment T3 provides a change back to the zero level of signal. During time segment T3 for the last transmission time slot, the change of signal level is of the same polarity as during time segment T1 of that last time slot. After the start of transmission, each transmission by either the transceiver or the transponder of a successive time segment signal level change is initiated only upon receipt from the other of a corresponding time segment signal change.

    Abstract translation: 自同步传输环路由收发器,应答器,用于从收发器发送到应答器的八个二进制数字组的数据链路,以及用于将来自转发器的一组八个二进制数字发送到收发器的数据链路 。 收发器和应答器中的每一个使用双极返回零直流信号格式,其中要发送的每个二进制数具有其自己的传输时隙,其被划分为三个基本相等的连续时间段T1,T2和T3。 时间段T1提供从零电平到二进制1的正极性(+1)和二进制0的负极性(-1)的单个单位电平信号的变化,时间段T2提供单个电平信号的单个单位电平信号的反转 时间段T1和时间段T3提供回到零电平的信号。 在最后一个传输时隙的时段T3期间,信号电平的改变与最后一个时隙的时间段T1具有相同的极性。 在传输开始之后,由接收机或应答器对连续时间段信号电平变化进行的每次发送仅在从对应的时间段信号变化的另一个接收到时才发起。

    Electrical circuit arrangements responsive to serial digital signals
forming multi-byte data-words
    46.
    发明授权
    Electrical circuit arrangements responsive to serial digital signals forming multi-byte data-words 失效
    响应于形成多字节数据字的串行数字信号的电路布置

    公开(公告)号:US4035601A

    公开(公告)日:1977-07-12

    申请号:US587695

    申请日:1975-06-17

    CPC classification number: H04L1/0078 H04L7/041 H04L7/044

    Abstract: Envisages the use of a format of serial digital signalling in which each data word comprises a predetermined number of bytes formed by bits of substantially uniform duration and in which each byte comprises a "start" bit of a first binary significance (e.g. 0) a "stop" bit having a second binary significance (e.g. 1) and an identical plurality of "data" bits immediately succeeding said "start" bit and in which the final byte of the data-word is characterized in that it has an additional bit having said first binary significance 0 interposed between last "data" bit and the "stop" bit thereof. The reading of that bit immediately succeeding the last "data" bit of each byte of each data-word of a transmission produce a so-called synchronizing pulse-sequence comprising bits of said second significance for all bytes except that last and a bit of said first significance for the last byte.A response circuit is provided normally to maintain byte-to-byte synchronization. If de-synchronization is detected the data-word involved is completely cancelled and the circuit is set for re-synchronization preparatory to commencement of next data-word.

    Abstract translation: 设想使用串行数字信号的格式,其中每个数据字包括由基本上均匀的持续时间的比特形成的预定数量的字节,并且其中每个字节包括第一二进制重要性的“起始”位(例如0) 停止“位具有第二二进制有效值(例如1)和紧邻所述”开始“位之后的相同多个”数据“位,并且其中数据字的最后字节的特征在于其具有所述 最后的“数据”位与其“停止”位之间插入第一个二进制值。 紧接在传输的每个数据字的每个字节的最后“数据”位之后的位的读取产生所谓的同步脉冲序列,所述同步脉冲序列包括对于所有字节的所述第二有效位的位,除了上述 最后一个字节的第一个意义。

    Circuit arrangement for data processing telephone exchange installations with systems for message transmission
    47.
    发明授权
    Circuit arrangement for data processing telephone exchange installations with systems for message transmission 失效
    数据处理电话交换机与电路传输系统的电路布置

    公开(公告)号:US3591722A

    公开(公告)日:1971-07-06

    申请号:US3591722D

    申请日:1969-02-24

    Applicant: SIEMENS AG

    Inventor: PALSA HELMUT

    CPC classification number: H04Q3/545 H04L1/0078 H04L1/0083

    Abstract: A circuit arrangement for telephone exchange installations wherein messages of different length are divided according to their length into a number of corresponding code signals of constant information volume for transmission in series over the same transmission path and consist of equally large groups of code elements, and wherein, prior to the code signals of a message, a length indicating signal indicative of the length of the message is transmitted to indicate the number of code signals corresponding to the message. First counter means presettable to an initial position by the length indicating signal and controllable to switch forward in pulse manner to a first predetermined position are used in conjunction with second counter means synchronously dependent on the switching forward of the first counter means and responsive thereto to be switched forward out of a second predetermined position. The second counter means have control outputs assigned to its counting positions that control the transmission and reception of code signals transmitted in series over the same transmission path from and to circuits individually assigned thereto. A comparator is responsive to the first counter means when the latter attains the first predetermined position to test the position of the second counter means and the received length indicating signal with regard to agreement.

    Management of message transmission using forward error correction

    公开(公告)号:US12040895B1

    公开(公告)日:2024-07-16

    申请号:US18069575

    申请日:2022-12-21

    Applicant: ITRON, INC.

    Abstract: Various embodiments disclosed herein provide techniques for deciding when to use FEC to transmit a message between node devices in a mesh network. In various embodiments, a method includes receiving, by a communication application executing on a first node of a mesh network, a message; determining, by the communication application, a second node in the mesh network to transmit the message to, the second node being a neighbor of the first node; determining, by the communication application based on a history of forward error correction (FEC) and non-FEC transmissions with the second node, that FEC or non-FEC should be used to transmit the message; and transmitting, by the communication application, in response to determining that FEC or non-FEC should be used to transmit the message, the message to the second node using FEC or non-FEC.

    Hardware-based dynamic cyclic-redundancy check (CRC) generator for automotive application

    公开(公告)号:US11949510B2

    公开(公告)日:2024-04-02

    申请号:US17929764

    申请日:2022-09-06

    CPC classification number: H04L1/0078 H04L1/0041 H04L1/0061 H04L12/40013

    Abstract: Embodiments include methods performed by a copy engine of a computing device for generating a cyclic redundancy check (CRC) in a safety network, including copying a first dataset received from an interface bus to obtain a first dataset copy, copying a second dataset received from the interface bus to obtain a second dataset copy, generating, via a first stream-wise CRC engine in the hardware of the copy engine, a first CRC value for the first dataset copy and, in parallel, generating, via a second stream-wise CRC engine in the hardware of the copy engine, a second CRC value for the second dataset copy, transmitting, to a processor of the computing device, a first stream-wise CRC message including the first dataset copy and the first CRC value, and a second stream-wise CRC message including the second dataset copy and the second CRC value.

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