RECEIVE PROCEDURE FOR EXTENDED LONG RANGE SUPPORTED DEVICES

    公开(公告)号:US20240348365A1

    公开(公告)日:2024-10-17

    申请号:US18636115

    申请日:2024-04-15

    Applicant: NXP USA, Inc.

    CPC classification number: H04L1/0045 H04L1/0061

    Abstract: Embodiments of receiver device and method are disclosed. In an embodiment, a receiver device comprises a wireless transceiver arranged to receive and transmit packets, and a controller operably coupled to the wireless transceiver to process the packets, wherein the controller is configured to receive a packet from a transmitter device and process the packet using one or more of dual correlators and dual finite state machines (FSMs), wherein the dual correlators include a first correlator to detect extended long-range (ELR) packets and a second correlator to detect non-ELR packets, and wherein the dual FSMs include a first FSM to process the ELR packets and a second FSM to process the non-ELR packets.

    Introduction and detection of erroneous stop condition in a single UART

    公开(公告)号:US12068854B2

    公开(公告)日:2024-08-20

    申请号:US17948616

    申请日:2022-09-20

    CPC classification number: H04L1/0082 H04L1/0041 H04L1/0045

    Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

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