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    Bit error rate reduction buffer
    41.
    发明授权
    Bit error rate reduction buffer 有权
    位错误率减少缓冲区

    公开(公告)号：US07783935B2

    公开(公告)日：2010-08-24

    申请号：US11445589

    申请日：2006-06-02

    Applicant: Larry J. Thayer

    Inventor： Larry J. Thayer

    IPC: G11B20/20 ,  G06F11/00 ,  G01R31/28 ,  G11C29/00 ,  H04W4/00 ,  H04B10/08

    CPC classification number: G06F13/4295 ,  G06F11/1004 ,  G06F13/1673 ,  G06F13/1684 ,  H04B10/40 ,  H04L1/0001 ,  H04L1/242 ,  H04L25/14 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive differential bit pair inputs to a plurality of FIFOs. The data is then driven from a parallel output of the plurality of FIFOs to the parallel input of a synchronizer. The data is then driven from the parallel output of the synchronizer to the parallel input of a serializer. The serializer, through different bit pair outputs, drives a second serial HSS link.

    Abstract translation: 在优选实施例中，本发明提供了一种用于减少误码率的电路。 数据恢复电路将数据从第一HSS链路恢复到差分位对输入。 来自数据恢复电路的差分位对输出的数据驱动差分位对输入到多个FIFO。 然后将数据从多个FIFO的并行输出驱动到同步器的并行输入。 然后将数据从同步器的并行输出驱动到串行器的并行输入。 串行器通过不同的位对输出驱动第二个串行HSS链路。

    Self-synchronizing pseudorandom bit sequence checker
    42.
    发明授权
    Self-synchronizing pseudorandom bit sequence checker 失效
    自同步伪随机比特序列检验器

    公开(公告)号：US07757142B2

    公开(公告)日：2010-07-13

    申请号：US12174327

    申请日：2008-07-16

    Applicant: Mohit Kapur ,  Seongwon Kim

    Inventor： Mohit Kapur ,  Seongwon Kim

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: H04L1/242

    Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

    Abstract translation: 提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。 被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。 在本发明的一个方面，PRBS检查技术包括以下步骤/操作。 对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。 错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。 然后，错误位的传播在后续的时钟周期被禁止。 禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

    VEHICLE HEALTH MANAGEMENT SYSTEM
    43.
    发明申请
    VEHICLE HEALTH MANAGEMENT SYSTEM 有权
    车辆健康管理系统

    公开(公告)号：US20100171630A1

    公开(公告)日：2010-07-08

    申请号：US12349643

    申请日：2009-01-07

    Applicant: Michael Alexander Carralero ,  Kirby J. Keller ,  Charles E. Morris

    Inventor： Michael Alexander Carralero ,  Kirby J. Keller ,  Charles E. Morris

    IPC: G08B7/00

    CPC classification number: G07C5/085 ,  B60R16/0232 ,  H04L1/242 ,  H04L2001/0094

    Abstract: A method, apparatus, and computer program product for processing health management data for a vehicle. A plurality of modulated signals is received on a bus system in the vehicle. The plurality of modulated signals contains health management data from a plurality of data acquisition units. Each modulated signal has a different frequency from another modulated signal in the plurality of modulated signals to form a plurality of frequencies. The plurality of frequencies is selected to avoid interference with other data transmitted over the bus system by a plurality of data processing systems in the vehicle. The plurality of modulated signals is processed based on the plurality of frequencies used to transmit the plurality of modulated signals.

    Abstract translation: 一种用于处理车辆健康管理数据的方法，装置和计算机程序产品。 在车辆中的总线系统上接收多个调制信号。 多个调制信号包含来自多个数据采集单元的健康管理数据。 每个调制信号具有与多个调制信号中的另一调制信号不同的频率，以形成多个频率。 选择多个频率以避免与车辆中的多个数据处理系统在总线系统上传输的其他数据的干扰。 基于用于发送多个调制信号的多个频率来处理多个调制信号。

    Method of detecting data transmission errors in a CAN controller, and a CAN controller for carrying out the method
    44.
    发明申请
    Method of detecting data transmission errors in a CAN controller, and a CAN controller for carrying out the method 有权
    检测CAN控制器中的数据传输错误的方法，以及用于执行该方法的CAN控制器

    公开(公告)号：US20100162090A1

    公开(公告)日：2010-06-24

    申请号：US12655841

    申请日：2010-01-08

    Applicant: Christoph Emde ,  Johannes Hesselbarth ,  Alexander Springer

    Inventor： Christoph Emde ,  Johannes Hesselbarth ,  Alexander Springer

    IPC: H03M13/00 ,  G06F11/10

    CPC classification number: H04L12/4135 ,  H04L1/242 ,  H04L12/40032 ,  H04L2012/40215

    Abstract: A method of detecting data transmission errors in a CAN controller includes generating at least one check bit that is verifiable for ensuring the consistency of the transmitted data. A CAN controller that ensures continuous error monitoring during data transmission includes an interface unit for exchanging data with a CAN bus, a memory unit for storing received data and data to be transmitted, and an electronic unit for controlling data transmission between the memory unit and the interface unit. The interface unit of the CAN controller has an arrangement for generating check bits for received data and for verifying check bits for data to be transmitted.

    Abstract translation: 检测CAN控制器中的数据传输错误的方法包括产生可验证的至少一个校验位，以确保所发送数据的一致性。 一种确保在数据传输期间连续进行错误监测的CAN控制器，包括用于与CAN总线交换数据的接口单元，用于存储所接收的数据和要发送的数据的存储单元，以及用于控制存储器单元和存储单元之间的数据传输的电子单元 接口单元。 CAN控制器的接口单元具有用于产生用于接收数据的校验位和用于验证要发送的数据的校验位的布置。

    Margin test methods and circuits
    46.
    发明授权
    Margin test methods and circuits 有权
    保证金测试方法和电路

    公开(公告)号：US07627029B2

    公开(公告)日：2009-12-01

    申请号：US10815604

    申请日：2004-03-31

    Applicant: Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

    Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

    IPC: H03H7/30 ,  H04L27/00

    CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

    Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

    Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。

    Bit error tester
    47.
    发明授权
    Bit error tester 有权
    位误差测试仪

    公开(公告)号：US07475304B1

    公开(公告)日：2009-01-06

    申请号：US11070576

    申请日：2005-02-25

    Applicant: Gary H. Kaufman ,  James P. Stephens, Sr. ,  George D. Gonczy

    Inventor： Gary H. Kaufman ,  James P. Stephens, Sr. ,  George D. Gonczy

    IPC: G01R31/28

    CPC classification number: G01R31/3171 ,  H04L1/242

    Abstract: A method and device for comparing two generic digital signals over a wide range of data rates and for counting the number of bit errors between digital signals under the conditions of noise and jamming. The bit error tester of the invention compares the digital signal sent with the digital signal received back from the unit under test and outputs the error signal. In the preferred arrangement of the invention, a field programmable gate array is used and a switch and LED display are used to introduce and monitor a time delay in the sent signal to ensure that the signals are in time alignment prior to comparison.

    Abstract translation: 一种用于在宽范围的数据速率上比较两个通用数字信号并用于在噪声和干扰条件下对数字信号之间的位错误数进行计数的方法和装置。 本发明的比特误差测试器将发送的数字信号与从被测单元接收的数字信号进行比较，并输出误差信号。 在本发明的优选布置中，使用现场可编程门阵列，并且使用开关和LED显示器来引入和监视所发送的信号中的时间延迟，以确保信号在比较之前处于时间对准。

    Self-Synchronizing Pseudorandom Bit Sequence Checker
    48.
    发明申请
    Self-Synchronizing Pseudorandom Bit Sequence Checker 失效
    自同步伪随机比特序列检测器

    公开(公告)号：US20080276139A1

    公开(公告)日：2008-11-06

    申请号：US12174327

    申请日：2008-07-16

    Applicant: Mohit Kapur ,  Seongwon Kim

    Inventor： Mohit Kapur ,  Seongwon Kim

    IPC: G01R31/3177 ,  G06F11/25

    CPC classification number: H04L1/242

    Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

    Abstract translation: 提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。 被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。 在本发明的一个方面，PRBS检查技术包括以下步骤/操作。 对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。 错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。 然后，错误位的传播在后续的时钟周期被禁止。 禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

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