公开(公告)号：US09653590B2

公开(公告)日：2017-05-16

申请号：US14747060

申请日：2015-06-23

Applicant: FUJITSU LIMITED

Inventor： Junji Kotani

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66462 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/1075 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/7787

Abstract: A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.

公开(公告)号：US09653548B2

公开(公告)日：2017-05-16

申请号：US15135262

申请日：2016-04-21

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/201 ,  H01L29/66 ,  B82Y99/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

公开(公告)号：US09653464B1

公开(公告)日：2017-05-16

申请号：US15264688

申请日：2016-09-14

Applicant: International Business Machines Corporation

Inventor： Effendi Leobandung

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/201 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L27/1211 ,  H01L21/30612 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41791 ,  H01L29/7848

Abstract: A method for forming a semiconductor device, including forming one or more fin structures on a semiconductor substrate, where the fin structure defines source and drain regions. The method includes forming a gate stack, depositing a first contact insulator layer, and applying an etching process to portions of the first insulator layer to form a trench that extends to the source region. The method also includes depositing an epitaxial lower band gap source material into the trench and extending to the source region, depositing a second insulator layer, applying a second etching process to portions of the second insulator layer to form a trench that extends to the source and drain regions, and depositing a metalizing material over the substrate.

公开(公告)号：US09653308B2

公开(公告)日：2017-05-16

申请号：US14839755

申请日：2015-08-28

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Devendra K. Sadana ,  Leathen Shi ,  Kuen-Ting Shiu

IPC: H01L21/306 ,  H01L21/02 ,  H01L29/201

CPC classification number: H01L21/30617 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/0273 ,  H01L21/30612 ,  H01L21/67086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7813 ,  H01L29/20 ,  H01L29/201 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.

公开(公告)号：US09608103B2

公开(公告)日：2017-03-28

申请号：US14505304

申请日：2014-10-02

Applicant: Toshiba Corporation

Inventor： Jeffrey Craig Ramer ,  Karl Knieriem

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/201 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

公开(公告)号：US09601609B2

公开(公告)日：2017-03-21

申请号：US14569492

申请日：2014-12-12

Applicant: Renesas Electronics Electronics

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L29/40 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: Characteristics of a semiconductor device are improved.A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.

公开(公告)号：US09583588B2

公开(公告)日：2017-02-28

申请号：US14533864

申请日：2014-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  King-Yuen Wong ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC: H01L29/778 ,  H01L29/06 ,  H01L21/335 ,  H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/20 ,  H01L21/02 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/201 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/2258 ,  H01L21/3065 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0843 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/7787

Abstract: A method includes epitaxially growing a gallium nitride (GaN) layer over a silicon substrate. The method further includes epitaxially growing a donor-supply layer over the GaN layer. The method further includes forming a source and a drain on the donor-supply layer. The method further includes forming a gate structure between the source and the drain on the donor-supply layer. The method further includes plasma etching a portion of a drift region of the donor-supply layer to a depth of less than 60% of a donor-supply layer thickness. The method further includes depositing a dielectric layer over the donor-supply layer.

Abstract translation: 一种方法包括在硅衬底上外延生长氮化镓（GaN）层。 该方法还包括在GaN层上外延生长施主供体层。 该方法还包括在供体层上形成源极和漏极。 该方法还包括在供体层上的源极和漏极之间形成栅极结构。 该方法还包括将供体供体层的漂移区域的一部分等离子体蚀刻到小于施主供体层厚度的60％的深度。 该方法还包括在供体供体层上沉积介电层。

公开(公告)号：US09583562B2

公开(公告)日：2017-02-28

申请号：US14745146

申请日：2015-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joel P. de Souza ,  Jeehwan Kim ,  Devendra K. Sadana ,  Brent A. Wacaser

IPC: H01L33/00 ,  H01L29/06 ,  H01L29/24 ,  H01L29/201 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/207

CPC classification number: H01L29/267 ,  H01L29/0607 ,  H01L29/0634 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/2206 ,  H01L29/227 ,  H01L29/24 ,  H01L29/263 ,  H01L29/66204 ,  H01L29/66219 ,  H01L29/66522 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/861 ,  H01L29/8613

Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm−2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

Abstract translation: 半导体器件包括半导体衬底和形成在位错密度超过108cm -2的衬底上的p掺杂层。 在p掺杂层上或其中形成n型层。 n型层包括II-VI材料，其被配置为在具有III-V n型层的器件上容忍位错密度以形成具有减小的漏电流的电子器件。

公开(公告)号：US09559183B2

公开(公告)日：2017-01-31

申请号：US14271277

申请日：2014-05-06

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/336 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件具有衬底，其上具有缓冲层，沟道层，阻挡层，穿透其中并到达沟道层内部的沟槽，通过栅极绝缘膜放置在沟槽中的栅电极，以及漏极和源极 位于栅电极两侧的阻挡层上的电极。 栅极绝缘膜具有由第一绝缘膜形成并从沟槽的端部延伸至漏极侧的第一部分和由第一绝缘膜和第二绝缘膜构成的第二部分，并且设置在漏电极侧 相对于第一部分。 可以通过减小在漏电极侧的沟槽的端部处的第一部分的厚度来减小导通电阻。

公开(公告)号：US09543393B2

公开(公告)日：2017-01-10

申请号：US13834871

申请日：2013-03-15

Applicant: SixPoint Materials, Inc. ,  Seoul Semiconductor Co., Ltd.

Inventor： Tadao Hashimoto ,  Edward Letts ,  Sierra Hoff

IPC: H01L29/201 ,  H01L29/20 ,  C30B7/10 ,  C30B29/40 ,  C30B33/10 ,  H01L21/02 ,  C30B33/00

CPC classification number: H01L29/201 ,  C30B7/105 ,  C30B29/403 ,  C30B29/406 ,  C30B33/00 ,  C30B33/10 ,  H01L21/02013 ,  H01L21/02019 ,  H01L29/2003

Abstract: The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers.

Abstract translation: 本发明公开了一种III族氮化物晶片，例如GaN，AlN，InN及其合金，其一面在视觉上与其他表面不同。 在用诸如多线锯的机械方法从III族氮化物的块状晶体切片晶片之后，晶片被化学蚀刻，使得晶片的一个表面在视觉上与另一表面区分开。 本发明还公开了一种制造这种晶片的方法。