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公开(公告)号：US12210373B2
公开(公告)日：2025-01-28
申请号：US18165855
申请日：2023-02-07
Applicant: STMicroelectronics International N.V.
Inventor： Ankur Bal , Sharad Gupta , Anupam Jain
Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.
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公开(公告)号：US20250028653A1
公开(公告)日：2025-01-23
申请号：US18776561
申请日：2024-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Jawad BENHAMMADI
Abstract: A method of securization of programs in a memory embedded within a microcontroller includes writing a boot program into a first area of the memory and writing at least one additional program into at least one second area of the memory. One or more values of a first register are modified to provide a write protection of the first and second areas. A prohibition against modification of the one or more values of the first register is then implemented when those values are associated with a write protection state of the first area.
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公开(公告)号：US12205650B2
公开(公告)日：2025-01-21
申请号：US18173472
申请日：2023-02-23
Inventor： Francesco La Rosa , Marco Bildgen
Abstract: An integrated circuit comprises a memory device including a memory plane having non-volatile memory cells and being non-observable in read mode from outside the memory device, a controller, internal to the memory device, configured to detect the memorized content of the memory plane, and when the memorized content contains locking content, automatically lock any access to the memory plane from outside the memory device, the integrated circuit then being in a locked status, and authorize delivery outside the memory device of at least one sensitive datum stored in the memory plane.
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公开(公告)号：US12204782B2
公开(公告)日：2025-01-21
申请号：US18337751
申请日：2023-06-20
Applicant: STMicroelectronics International N.V.
Inventor： Urmishkumar Karsanbhai Patel , Danish Hasan Syed , Prateek Singh
IPC: G06F3/06
Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.
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公开(公告)号：US20250023531A1
公开(公告)日：2025-01-16
申请号：US18352034
申请日：2023-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Vratislav Michal
Abstract: A circuit includes a current source, a differential pair of transistors coupled to the current source, an active load, and a current injection circuit. The differential pair of transistors has a first offset voltage and an input transconductance. The current injection circuit is configured to supply a first current and a second current to produce a second offset voltage across the differential pair of transistors opposite the first offset voltage. The first current and the second current has a same thermal dependence as the input transconductance of the differential pair of transistors.
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Patent Agency Ranking
公开(公告)号：US20250015795A1
公开(公告)日：2025-01-09
申请号：US18750277
申请日：2024-06-21
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Atul DWIVEDI
Abstract: An integrated circuit comprises a current source, a plurality of parallel transistors, a plurality of switches, switch control circuitry, and measurement circuitry. Each switch selectively couples the current source to a corresponding transistor. The switch control circuitry is configured to, at different times, cause all the switches to close and, separately for each transistor, cause the switch associated with each transistor to close while causing all other switches to open. The measurement circuitry is configured to measure, separately for each of the transistors, a base-emitter voltage (VBE) when all the switches are closed and a VBE when only the switch associated with each transistor is closed, determine a ΔVBE for each of the plurality of transistors by calculating a difference between the VBE when only the switch associated with each transistor is closed and the VBE when all the switches are closed, and calculate an average of all the ΔVBEs.
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公开(公告)号：US20250007526A1
公开(公告)日：2025-01-02
申请号：US18345298
申请日：2023-06-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , INSTITUT POLYTECHNIQUE DE BORDEAUX , UNVERSITE DE BORDEAUX
Inventor： Denis Michael FLORES PAZOS , Andreia CATHELIN , Yann DEVAL
Abstract: In various embodiments, a frequency dividing circuit is provided. The frequency dividing circuit may include a first circuit including an m-bit multiplexer configured to receive a positive binary word and a negative binary word as inputs. The frequency dividing circuit may receive a controlled oscillator output signal and a complement of the controlled oscillator output signal, generate a frequency dividing circuit output signal from the controlled oscillator output signal and the complement of the controlled oscillator output signal using the positive binary word and the negative binary word. A ratio of the frequency dividing circuit output signal frequency to the controlled oscillator output signal frequency is a decimal value greater than zero and less than one and is determined using a ratio of a value of the positive binary word to a sum of the value of the positive binary word and an absolute value of the negative binary word.
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公开(公告)号：US20250007463A1
公开(公告)日：2025-01-02
申请号：US18751595
申请日：2024-06-24
Applicant: STMicroelectronics International N.V.
Inventor： Raffaele Enrico FURCERI , Marco ZAMPROGNO
Abstract: Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.
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公开(公告)号：US20250006267A1
公开(公告)日：2025-01-02
申请号：US18753094
申请日：2024-06-25
Applicant: STMicroelectronics International N.V.
Inventor： Radouane Habhab , Vincenzo Della Marca , Nadia Miridi ép Seroschtanoff , Pascal Masson , Franck Melul , Madjid Akbal
IPC: G11C16/10 , H01L29/423 , H10B43/27
Abstract: The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.
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公开(公告)号：US20250002333A1
公开(公告)日：2025-01-02
申请号：US18215322
申请日：2023-06-28
Applicant: STMicroelectronics International N.V.
Inventor： Eric SAUGIER
Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.
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