公开(公告)号：US12204782B2

公开(公告)日：2025-01-21

申请号：US18337751

申请日：2023-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Urmishkumar Karsanbhai Patel ,  Danish Hasan Syed ,  Prateek Singh

IPC: G06F3/06

Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.

公开(公告)号：US20240427514A1

公开(公告)日：2024-12-26

申请号：US18337751

申请日：2023-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Urmishkumar Karsanbhai Patel ,  Danish Hasan Syed ,  Prateek Singh

IPC: G06F3/06

Abstract: According to an embodiment, a method for testing and repairing local memory in a hardware accelerator from a one-time programmable memory (OTP) is provided. The method includes asserting a grant signal, a loading of a first repair data for a sub-set of the local memory associated with a main-controller from a first partition of the OTP memory, communicating a status signal after completion of the loading indicating a completion of the loading, and de-asserting the grant signal in response to receiving the status signal.

公开(公告)号：US12265121B2

公开(公告)日：2025-04-01

申请号：US18322336

申请日：2023-05-23

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Shalini Pathak ,  Prateek Singh

IPC: G01R31/3181 ,  G01R31/3185

Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

公开(公告)号：US20240393393A1

公开(公告)日：2024-11-28

申请号：US18322336

申请日：2023-05-23

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Jain ,  Shalini Pathak ,  Prateek Singh

IPC: G01R31/3181 ,  G01R31/3185

Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.