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51.发明授权公开(公告)号：US12191235B2
公开(公告)日：2025-01-07
申请号：US18512567
申请日：2023-11-17
Inventor： Belgacem Haba , Rajesh Katkar
IPC: H01L23/473 , H01L23/00 , H01L23/427 , H01L23/498 , H01L25/18 , H10B80/00
Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.
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公开(公告)号：US20250006674A1
公开(公告)日：2025-01-02
申请号：US18497585
申请日：2023-10-30
Inventor： Cyprian Emeka Uzoh , Oliver Zhao , Gabriel Z. Guevara , Dominik Suwito , Rajesh Katkar
IPC: H01L23/00
Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.
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公开(公告)号：US20250006672A1
公开(公告)日：2025-01-02
申请号：US18379053
申请日：2023-10-11
Inventor： Cyprian Emeka Uzoh , Gaius Gillman Fountain, JR.
IPC: H01L23/00
Abstract: A first conductive feature of a first substrate is bonded to a second conductive feature of a second substrate. The first conductive feature is formed by depositing a conductive base layer on the first substrate, the first substrate having an opening formed therein, recessing the conductive base layer in the opening, and depositing a conductive surface layer on the recessed conductive base layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive feature and the second conductive feature.
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公开(公告)号：US20250006632A1
公开(公告)日：2025-01-02
申请号：US18401082
申请日：2023-12-29
Inventor： Xu CHANG , Rajesh KATKAR
IPC: H01L23/528 , H01L23/00 , H01L25/065
Abstract: An assembly may include a base element comprising a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer disposed on the frontside of the base substrate and including a signal pad to convey an electrical signal to the active circuitry. The assembly may further include a first functional element comprising a first semiconductor substrate having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element having a first contact feature to connect to power or ground, wherein the first bonding layer is hybrid bonded to the second bonding layer.
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公开(公告)号：US12176303B2
公开(公告)日：2024-12-24
申请号：US18346396
申请日：2023-07-03
Inventor： Javier A. DeLaCruz , Rajesh Katkar
IPC: H01L23/00
Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
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Patent Agency Ranking
56.发明授权公开(公告)号：US12176263B2
公开(公告)日：2024-12-24
申请号：US18620753
申请日：2024-03-28
Applicant: Adeia Semiconductor Bonding Technologies Inc
Inventor： Belgacem Haba , Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/46 , H01L23/00 , H01L23/34 , H01L23/373 , H01L23/48 , H01L23/498 , H01L23/24
Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.
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公开(公告)号：US12153222B2
公开(公告)日：2024-11-26
申请号：US18360193
申请日：2023-07-27
Inventor： Rajesh Katkar , Belgacem Haba
IPC: G02B27/01 , G02B27/10 , G02B27/14 , H01L25/075
Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
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公开(公告)号：US20240387439A1
公开(公告)日：2024-11-21
申请号：US18784724
申请日：2024-07-25
Inventor： Belgacem Haba , Laura Wills Mirkarimi , Javier A. DeLaCruz , Rajesh Katkar , Cyprian Emeka Uzoh , Guilian Gao , Thomas Workman
Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.
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59.发明申请公开(公告)号：US20240387323A1
公开(公告)日：2024-11-21
申请号：US18512547
申请日：2023-11-17
Inventor： Belgacem Haba , Rajesh Katkar
IPC: H01L23/473 , H01L23/00 , H01L23/427 , H01L23/498 , H01L25/18 , H10B80/00
Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.
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公开(公告)号：US20240379539A1
公开(公告)日：2024-11-14
申请号：US18782629
申请日：2024-07-24
Inventor： Cyprian Emeka Uzoh , Gaius Gillman Fountain, JR. , Jeremy Alfred Theil
IPC: H01L23/522 , H01L23/00 , H01L23/29 , H01L23/31
Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
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