中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

98 records (took 0.017 seconds)

    Optimized bandwith allocation mechanism between circuit slots and packet bit stream in a communication network
    52.
    发明授权
    Optimized bandwith allocation mechanism between circuit slots and packet bit stream in a communication network 失效
    在通信网络中优化电路槽和分组比特流之间的带宽分配机制

    公开(公告)号：US4819230A

    公开(公告)日：1989-04-04

    申请号：US77485

    申请日：1987-07-24

    Applicant: Jean Calvignac ,  Pierre Secondo

    Inventor： Jean Calvignac ,  Pierre Secondo

    IPC: H04Q11/04 ,  H04L12/64 ,  H04M11/00 ,  H04J3/26

    CPC classification number: H04L12/64

    Abstract: The invention relates to a mechanism to be used in an integrated packet/circuit switched telecommunication network. It allows instantaneously on a per slot basis, the re-allocation of unused bandwidth left by a circuit user source to the background packet flow, and allows giving it back to the circuit source as it resumes its activity. The circuit user data Cd are sent through the network during slots of frames which are assigned to the circuit users on a per- call basis. Interfacing means (30, 32) are provided to generate slot qualifying bits Caq which are set to a first value when the corresponding circuit users are active and to a second value when the corresponding cirucit users are inactive. These qualifying bits are transported through the network in correspondence with the slot they qualify and sensed to cause the slots having a Caq set to the second value to be filled with packet bits.

    Communication line scanning device for a communication controller
    53.
    发明授权
    Communication line scanning device for a communication controller 失效
    通讯控制器的通讯线扫描装置

    公开(公告)号：US4493051A

    公开(公告)日：1985-01-08

    申请号：US433609

    申请日：1982-10-12

    Applicant: Bernard Brezzo ,  Jean Calvignac ,  Richard Dambricourt ,  Andre Masclet ,  Jean-Pierre Sanche

    Inventor： Bernard Brezzo ,  Jean Calvignac ,  Richard Dambricourt ,  Andre Masclet ,  Jean-Pierre Sanche

    IPC: H04L29/04 ,  G06F13/00 ,  G06F13/38 ,  G06F3/04

    CPC classification number: G06F13/385

    Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

    Abstract translation: 在连接到控制存储器的控制存储器的控制下操作的行扫描装置，其中存储器位置区域被分配给每一行，用于通信控制器中的线路适配器，用于从或从终端接收或发送消息位 使用任何协议连接到线路。 它包括第一存储器，其包括第一存储器和第二存储器，被分配给可以在同一时间读取和写入的每个存储器中的每一行的区域以及包括单个存储器的第二存储器，其中存储位置 区域被分配到每一行。 这些存储器由控制和地址单元寻址，该控制和地址单元在基本时间计数器的控制下包括第一和第二地址计数器，第一计数器在时间t内输出与第一存储有关的地址信息用于扫描行， 计数器在时间nt，n至少等于4时输出相对于第二存储器的地址信息，以及控制电路，其接收所述地址信息和用于在控制和地址单元的输出处提供存储器地址和读取的基本时间信息 在扫描期间选择的时间顺序地写入控制信息，扫描的当前行的地址。

    PROGRAMMABLE MULTIFIELD PARSER PACKET
    54.
    发明申请
    PROGRAMMABLE MULTIFIELD PARSER PACKET 失效
    可编程多路复用器分组

    公开(公告)号：US20120195208A1

    公开(公告)日：2012-08-02

    申请号：US13017963

    申请日：2011-01-31

    Applicant: Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    Inventor： Francois Abel ,  Jean Calvignac ,  Christoph Hagleitner ,  Jan van Lunteren ,  Fabrice Verplanken

    IPC: H04L12/26 ,  H04J3/24

    CPC classification number: H04L69/22

    Abstract: A method of operating a packet parser in a computing system includes providing a configurable packet pointer by the packet parser, the packet pointer configured to index a configurable number of atomic parsing elements, the atomic parsing elements having a configurable size, in a data stream received by the computing system for extraction, wherein the indexed atomic parsing elements are non-contiguous in the data stream; and receiving the extracted indexed atomic parsing elements from the data stream by the packet parser.

    Abstract translation: 一种在计算系统中操作分组解析器的方法包括：由分组解析器提供可配置的分组指针，所述分组指针被配置为在接收的数据流中索引可配置数量的原子解析元素（所述原子解析元素具有可配置大小） 由所述计算系统提取，其中所述索引的原子解析元素在所述数据流中不连续; 以及由分组解析器从数据流接收提取的索引原子解析元素。

    SELECTIVE HEADER FIELD DISPATCH IN A NETWORK PROCESSING SYSTEM
    56.
    发明申请
    SELECTIVE HEADER FIELD DISPATCH IN A NETWORK PROCESSING SYSTEM 有权
    网络处理系统中的选择头部现场分配

    公开(公告)号：US20080013541A1

    公开(公告)日：2008-01-17

    申请号：US11776807

    申请日：2007-07-12

    Applicant: Jean Calvignac ,  Gordon Davis

    Inventor： Jean Calvignac ,  Gordon Davis

    IPC: H04L12/54

    CPC classification number: H04L49/602 ,  H04L49/354 ,  H04L49/604 ,  H04L69/22

    Abstract: A method and structure are disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiples of such dispatch messages are bundled into a single composite dispatch message. Thus, selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

    Abstract translation: 公开了一种用于将适当数据发送到网络处理系统的方法和结构，所述网络处理系统包括用于提取网络处理器使用的协议头域的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 这种分派消息的倍数被捆绑成单个复合调度消息。 因此，来自N个分组的选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以引导入队 并且对N个分组的束进行帧改变。

    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms
    57.
    发明申请
    Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms 有权
    接收具有高效队列流控制，段放置和虚拟化机制的队列设备

    公开(公告)号：US20060259644A1

    公开(公告)日：2006-11-16

    申请号：US11487265

    申请日：2006-07-14

    Applicant: William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    Inventor： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    IPC: G06F15/16

    CPC classification number: H04L69/16 ,  H04L69/12 ,  H04L69/161

    Abstract: A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ. The number of entries available in the RWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ.

    Abstract translation: 一种用于卸载分裂（例如，分裂式插座，拆分式iSCSI，拆分式DAFS）堆栈环境中接收队列管理的机制，包括有效的队列流控制和TCP / IP重传支持。 上层协议（ULP）创建互联网协议套件卸载引擎（IPSOE）和ULP利用的接收工作队列和完成队列，以传输信息并执行发送操作。 当消费者开始接收操作时，接收工作队列条目（RWQE）由ULP创建并写入接收工作队列（RWQ）。 通知ISPOE对RWQ的新条目，并随后读取包含要接收的数据的指针的该条目。 接收到数据后，IPSOE创建写入完成队列（CQ）的完成队列条目（CQE）。 在编写CQE之后，ULP随后处理该条目并将其从CQE中移除，释放了RWQ和CQ两者中的空间。 RWQ中可用的条目数由ULP监视，以便它不会覆盖任何有效的条目。 同样，IPSOE监视CQ中可用条目的数量，以免覆盖CQ。

    Systems and methods for rate-limited weighted best effort scheduling
    58.
    发明申请
    Systems and methods for rate-limited weighted best effort scheduling 失效

    公开(公告)号：US20060245443A1

    公开(公告)日：2006-11-02

    申请号：US11119329

    申请日：2005-04-29

    Applicant: Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    Inventor： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

    IPC: H04L12/28 ,  G01R31/08

    CPC classification number: H04L47/623 ,  H04L47/50 ,  H04L47/568

    Abstract: Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.

Patent Agency Ranking