公开(公告)号：US20100080044A1

公开(公告)日：2010-04-01

申请号：US12570159

申请日：2009-09-30

Applicant: Hyeoung-won SEO ,  Young-yong BYUN ,  Seong-jin JANG ,  Sang-woong SHIN ,  Soo-ho SHIN ,  Won-woo LEE ,  Jeong-soo PARK

Inventor： Hyeoung-won SEO ,  Young-yong BYUN ,  Seong-jin JANG ,  Sang-woong SHIN ,  Soo-ho SHIN ,  Won-woo LEE ,  Jeong-soo PARK

IPC: G11C11/24 ,  G11C8/00 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract translation: 根据一些本发明的概念，半导体存储器件可以包括多个存储单元块，其包括具有位线的第一存储器单元块，边沿读出放大器块，包括耦合到第一位的位线的一部分的边沿读出放大器 存储单元块和耦合到边缘读出放大器的平衡电容单元。

公开(公告)号：US20100041661A1

公开(公告)日：2010-02-18

申请号：US12514244

申请日：2007-10-26

Applicant: Hye Kyung Chang ,  Yeong Soo Oh ,  Yong Jin Jang ,  Sung Sub Kim ,  Kyeong Sik Min ,  Chul Woong Chung ,  Mi Jeong Park ,  Jung Gyu Park

Inventor： Hye Kyung Chang ,  Yeong Soo Oh ,  Yong Jin Jang ,  Sung Sub Kim ,  Kyeong Sik Min ,  Chul Woong Chung ,  Mi Jeong Park ,  Jung Gyu Park

IPC: C07D237/00

CPC classification number: C07D237/14

Abstract: The present invention relates to a pyridazinone derivative which can be used as a caspase inhibitor, process for the preparation thereof, and pharmaceutical composition for inhibiting caspase comprising the same.

Abstract translation: 本发明涉及可用作胱天蛋白酶抑制剂的哒嗪酮衍生物，其制备方法，以及用于抑制包含其的半胱天冬酶的药物组合物。

公开(公告)号：US07663413B2

公开(公告)日：2010-02-16

申请号：US11483422

申请日：2006-07-07

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K17/6872 ,  H03K17/161 ,  Y10T307/74

Abstract: A line driver circuit for stabilizing a signal that is output through a transmission line, wherein the line driver circuit receives a first signal having a first swing width corresponding to a difference between a first voltage and a second voltage, creates a second signal having a second swing width less than the first swing width, and outputs the second signal through a transmission line. The line driver circuit includes: a pull-up circuit that pulls up the second signal to a high level; a pull-down circuit that is connected to the pull-up circuit and pulls down the second signal to a low level; and an initializing circuit that is connected to a node of the transmission line, outputs a signal having a voltage of the low level or the high level to the node of the transmission line, and initializes the voltage at the node of the transmission line to the low level or the high level.

Abstract translation: 一种用于稳定通过传输线输出的信号的线路驱动器电路，其中线路驱动电路接收具有与第一电压和第二电压之间的差对应的第一摆幅宽度的第一信号，产生具有第二信号的第二信号 摆动宽度小于第一摆动宽度，并通过传输线输出第二信号。 线路驱动电路包括：将第二信号拉高至高电平的上拉电路; 下拉电路，连接到上拉电路并将第二信号拉低至低电平; 以及连接到传输线节点的初始化电路，将具有低电平或高电平的电压的信号输出到传输线的节点，并将传输线节点处的电压初始化为 低水平或高水平。

公开(公告)号：US07659185B2

公开(公告)日：2010-02-09

申请号：US10570285

申请日：2004-09-02

Applicant: Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

Inventor： Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

IPC: H01L21/20

CPC classification number: H01L21/02532 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02672 ,  H01L27/1277 ,  H01L29/78603

Abstract: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) is formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.

Abstract translation: 公开了一种在基板上形成硅薄膜的方法，更具体地说，涉及一种在柔性金属基板上形成质量好的多晶硅薄膜的方法。 准备金属基板（110），使金属基板（110）的表面变平。 在金属基板（110）上形成绝缘膜（120）。 在绝缘膜（120）上形成非晶硅层（130）。 金属层（140）形成在非晶硅层（130）上。 将金属基板（110）上的样品加热并结晶。

公开(公告)号：US07619935B2

公开(公告)日：2009-11-17

申请号：US11680886

申请日：2007-03-01

Applicant: Kyoung Ho Kim ,  Seong Jin Jang

Inventor： Kyoung Ho Kim ,  Seong Jin Jang

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/18 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/002

Abstract: A circuit and method are provided for controlling the gate voltage of a transistor acting between local and global input/output lines of a memory device, the circuit including a local input/output line, a local from/to global input/output multiplexer in signal communication with the local input/output line, a global input/output line in signal communication with the local from/to global input/output multiplexer, and a local from/to global input/output controller having an input node and an output node, the input node disposed for receiving a signal indicative of an input or output operation, and the output node in signal communication with a gate of the local from/to global input/output multiplexer for providing a gate signal of a first or second level in the presence of the output operation, and a gate signal of a third level in the presence of the input operation.

Abstract translation: 提供了一种电路和方法，用于控制在存储器件的局部和全局输入/输出线之间起作用的晶体管的栅极电压，该电路包括本地输入/输出线，本地输入/输出多路复用器的本地信号 与本地输入/输出线的通信，与本地从/到全局输入/输出多路复用器进行信号通信的全局输入/输出线，以及具有输入节点和输出节点的本地输入/输出控制器， 所述输入节点被设置用于接收指示输入或输出操作的信号，并且所述输出节点与所述本地输入/输出多路复用器的门相信号通信，以在所述输入/输出多路复用器中提供第一或第二电平的门信号 在存在输入操作的情况下存在输出操作和第三级的门信号。

公开(公告)号：US07609584B2

公开(公告)日：2009-10-27

申请号：US11594807

申请日：2006-11-09

Applicant: Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

Inventor： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

Abstract translation: 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20090214251A1

公开(公告)日：2009-08-27

申请号：US12206003

申请日：2008-09-08

Applicant: Jong In KIM ,  Myoung Su Baek ,  Sung Gi Kim ,  Ho Jin Jang

Inventor： Jong In KIM ,  Myoung Su Baek ,  Sung Gi Kim ,  Ho Jin Jang

IPC: G03G21/00

CPC classification number: G03G21/1832 ,  G03G21/12 ,  G03G2221/1609

Abstract: An image forming apparatus includes an image carrier, an exposure unit to form a latent image on the image carrier by light, and a particle entering prevention device to prevent particles from entering an optical path between the exposure unit and the image carrier. The particle entering prevention device includes a particle storage unit disposed in a vicinity of the optical path, to store the particles therein.

Abstract translation: 图像形成装置包括图像载体，用于通过光在图像载体上形成潜像的曝光单元和防止颗粒进入曝光单元和图像载体之间的光路的颗粒进入防止装置。 颗粒进入防止装置包括设置在光路附近的颗粒存储单元，用于将颗粒存储在其中。

公开(公告)号：US07546497B2

公开(公告)日：2009-06-09

申请号：US11419155

申请日：2006-05-18

Applicant: Seong-Jin Jang

Inventor： Seong-Jin Jang

IPC: G11C29/34 ,  G11C29/50

CPC classification number: G11C29/14 ,  G11C29/12015 ,  G11C29/32

Abstract: A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array.

Abstract translation: 半导体存储器件包括串行到并行转换器，其被配置为响应于处于第一模式的第一串行数据速率的第一串行数据以并行数据速率产生并行数据，并且被配置为响应于并行数据速率以并行数据速率生成并行数据 以第二模式的第二串行数据速率的第二串行数据，其中所述第二串行数据速率小于所述第一串行数据速率，以及数据写入电路，被配置为将并行数据提供给存储器单元阵列。

公开(公告)号：US07544145B2

公开(公告)日：2009-06-09

申请号：US11582025

申请日：2006-10-17

Applicant: Wook Jin Jang

Inventor： Wook Jin Jang

IPC: F16H3/62

CPC classification number: F16H3/663 ,  F16H3/66 ,  F16H2200/0056 ,  F16H2200/006 ,  F16H2200/0091 ,  F16H2200/201 ,  F16H2200/2012 ,  F16H2200/2048

Abstract: A power train of an automatic transmission has eight forward gear stages and three reverse gear stages. The power train includes two composite planetary gear sets and seven engagement elements: two clutches and five brakes. Two of the engagement elements are engaged in each gear stage.

Abstract translation: 自动变速器的动力传动系具有八个前进档和三个倒档档。 动力传动系包括两个复合行星齿轮组和七个接合元件：两个离合器和五个制动器。 两个接合元件啮合在每个档位。

公开(公告)号：US07541947B2

公开(公告)日：2009-06-02

申请号：US11802886

申请日：2007-05-25

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

IPC: H03M7/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.