公开(公告)号：US20070040247A1

公开(公告)日：2007-02-22

申请号：US11503269

申请日：2006-08-14

Applicant: Jong-Joo Lee ,  Mee-Hyun Ahn

Inventor： Jong-Joo Lee ,  Mee-Hyun Ahn

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.

Abstract translation: 本发明提供了各种引线框封装，其中信号连接和固定电压连接被配置为不同以改善连接相对于其分配的功能的相对性能。 信号连接包括一个或多个信号引线和对应的信号接合线的配置，其倾向于减小信号连接器的相对电容，从而提高高速性能。 固定电压连接包括固定电压引线和固定电压接合线的配置，这将降低固定电压连接器的电感，并降低固定电压连接上的噪声，并提高功率输送特性。 相关联的信号和固定电压连接的配置将趋于导致信号连接，其包括与相应的固定电压引线相比更短，更窄和/或更广泛地与半导体芯片的有源表面分离的信号引线。

公开(公告)号：US20070029662A1

公开(公告)日：2007-02-08

申请号：US11335523

申请日：2006-01-20

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/52

CPC classification number: H01L23/5228 ,  H01L23/5225 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.

Abstract translation: 半导体器件可以具有多个电介质层和介电层之间的至少一个终端电路线。 终端电路线可以形成在半导体衬底的有源表面上。

公开(公告)号：US20060134833A1

公开(公告)日：2006-06-22

申请号：US11289665

申请日：2005-11-28

Applicant: Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC: H01L21/48

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

公开(公告)号：US09165893B2

公开(公告)日：2015-10-20

申请号：US13229193

申请日：2011-09-09

Applicant: Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

Inventor： Yong-Hoon Kim ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC: H04B5/00 ,  H01L23/64 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Abstract translation: 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US08853854B2

公开(公告)日：2014-10-07

申请号：US13221494

申请日：2011-08-30

Applicant: Jong-Joo Lee

Inventor： Jong-Joo Lee

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.

Abstract translation: 半导体封装可以包括封装衬底，第一半导体芯片和第二半导体芯片。 第一半导体芯片可以布置在封装衬底上。 第一半导体芯片可以具有电连接到封装基板的插头和布置在插头周围的至少一个绝缘孔。 第二半导体芯片可以布置在第一半导体芯片上。 第二半导体芯片可以电连接到插头。 因此，绝缘孔和绝缘构件可以确保插头和第一半导体芯片之间以及插头之间的电隔离。

公开(公告)号：US08723315B2

公开(公告)日：2014-05-13

申请号：US13470572

申请日：2012-05-14

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US08633579B2

公开(公告)日：2014-01-21

申请号：US13208455

申请日：2011-08-12

Applicant: Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

Inventor： Un-Byoung Kang ,  Jong-Joo Lee ,  Yong-Hoon Kim ,  Tae-Hong Min

IPC: H01L23/02

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract translation: 多芯片封装可以包括封装衬底，插入器芯片，第一半导体芯片，散热结构和第二半导体芯片。 插入器芯片可以安装在封装衬底上。 第一半导体芯片可以安装在插入器芯片上。 第一半导体芯片的尺寸可以小于插入器芯片的尺寸。 散热结构可以布置在插入器芯片上以围绕第一半导体芯片。 散热结构可以将第一半导体芯片中的热量传递到插入器芯片。 第二半导体芯片可以安装在第一半导体芯片上。 因此，可以通过散热线将第一半导体芯片中的热量有效地传递到插入器芯片。

公开(公告)号：US08309372B2

公开(公告)日：2012-11-13

申请号：US13014108

申请日：2011-01-26

Applicant: Jong-joo Lee

Inventor： Jong-joo Lee

IPC: H01L21/66

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.

Abstract translation: 制造堆叠半导体封装的方法，其中堆叠多个半导体芯片包括制备包括第一半导体器件，第一穿透电极和第一连接单元的第一半导体芯片，该第一半导体芯片电连接到第一半导体器件或第一穿透 电极，将第一半导体芯片与第一连接单元插入到基底基板之间，通过使用打印方法在第一半导体芯片上形成第一重新布线图案和第一保护层，其中第一重新布线图案电连接到 第一穿透电极和第一保护层部分地覆盖第一重新布线图案并暴露第一重新布线图案的其他部分，并且将包括第二半导体器件的第二半导体芯片附接到第一半导体芯片以将第二半导体器件电连接到第一 重新布线图案

公开(公告)号：US20120223427A1

公开(公告)日：2012-09-06

申请号：US13470572

申请日：2012-05-14

Applicant: Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

Inventor： Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US20110309475A1

公开(公告)日：2011-12-22

申请号：US13080042

申请日：2011-04-05

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L29/94

CPC classification number: H01L27/0688 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  G11C8/06 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.

Abstract translation: 包括多个堆叠层的三维（3D）半导体器件和电连接多个层的贯穿硅通孔（TSV），其中在多个层之间的信号传输中，TSV发送摆动的信号 从高于接地电压的偏移电压到电源电压的范围，从而最小化TSV的金属氧化物半导体（MOS）电容的影响。