Dual damascene process and structure with dielectric barrier layer

    公开(公告)号:US6140220A

    公开(公告)日:2000-10-31

    申请号:US349843

    申请日:1999-07-08

    Applicant: Kang-Cheng Lin

    Inventor: Kang-Cheng Lin

    Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

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