公开(公告)号：US20150214162A1

公开(公告)日：2015-07-30

申请号：US14604525

申请日：2015-01-23

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Yu-Wen HU ,  Bai-Yao LOU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Hsin KUAN

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract translation: 无源元件结构的制造方法包括以下步骤。 保护层形成在基板上，并且基板的接合焊盘分别通过保护层开口露出。 在接合焊盘和保护层上形成导电层。 在导电层上形成图案化的光致抗蚀剂层，并且与保护层开口相邻的导电层通过光致抗蚀剂层开口露出。 铜凸块分别电镀在导电层上。 除去未被铜凸块覆盖的光致抗蚀剂层和导电层。 在铜凸块和保护层上形成钝化层，并通过钝化层开口露出至少一个铜凸块。 扩散阻挡层和氧化阻挡层依次化学镀在铜凸块上。

公开(公告)号：US09064950B2

公开(公告)日：2015-06-23

申请号：US14135506

申请日：2013-12-19

Applicant: XINTEC INC.

Inventor： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

IPC: H01L21/78 ,  B81C1/00

CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

公开(公告)号：US09054114B2

公开(公告)日：2015-06-09

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US09030011B2

公开(公告)日：2015-05-12

申请号：US13959567

申请日：2013-08-05

Applicant: Xintec Inc.

Inventor： Chao-Yen Lin ,  Yi-Hang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：载体基板; 具有上表面和下表面的半导体衬底，设置在载体衬底上; 位于所述半导体衬底的上表面上的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US20150123285A1

公开(公告)日：2015-05-07

申请号：US14592840

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Po-Han LEE

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract translation: 提供了一种芯片器件封装及其制造方法。 芯片器件封装包括具有第一表面和相对的第二表面的半导体衬底。 凹部与半导体衬底的侧壁相邻地设置，从半导体衬底的第一表面延伸到半导体衬底的至少第二表面。 保护层设置在半导体衬底的第一表面和凹部中。 在半导体衬底的第一表面上设置通孔。 与保护层的材料不同的缓冲材料设置在通孔中并被保护层覆盖。

公开(公告)号：US20150097286A1

公开(公告)日：2015-04-09

申请号：US14568056

申请日：2014-12-11

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/20 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2221/68327 ,  H01L2221/68386 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02377 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11334 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate.

Abstract translation: 芯片封装包括封装基板，半导体芯片和多个导电结构。 半导体芯片具有围绕中心区域的中心区域和边缘区域。 导电结构位于封装衬底和半导体芯片之间。 导电结构具有不同的高度，并且导电结构的高度从半导体芯片的中心区域逐渐增加到半导体芯片的边缘区域，使得半导体芯片的边缘区域与封装基板之间的距离 大于半导体芯片的中心区域和封装基板之间的距离。

公开(公告)号：US08975755B2

公开(公告)日：2015-03-10

申请号：US14171734

申请日：2014-02-03

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。

公开(公告)号：US08951836B2

公开(公告)日：2015-02-10

申请号：US14214389

申请日：2014-03-14

Applicant: Xintec Inc.

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L21/44 ,  H01L21/768 ,  B81B7/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a chip package, in which a substrate has a plurality of conducting pads located below its lower surface, and a dielectric layer located between the conducting pads. A hole is formed extending from the upper surface of the substrate towards the conducting pads. After the hole is formed, a trench is formed extending from the upper surface towards the lower surface of the substrate, with the trench connecting with the hole. An insulating layer is formed on a sidewall of the trench and a sidewall and a bottom of the hole, and a portion of the insulating layer and a portion of the dielectric layer are removed to expose a portion of the conducting pads. A conducting layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole, electrically contacting with the conducting pads.

Abstract translation: 一种用于形成芯片封装的方法，其中衬底具有位于其下表面下方的多个导电焊盘以及位于导电焊盘之间的电介质层。 形成从衬底的上表面朝向导电垫延伸的孔。 在形成孔之后，形成从衬底的上表面向下表面延伸的沟槽，沟槽与孔连接。 绝缘层形成在沟槽的侧壁和孔的侧壁和底部上，绝缘层的一部分和电介质层的一部分被去除以暴露导电垫的一部分。 导电层形成在沟槽的侧壁和孔的侧壁和底部，与导电垫电接触。

公开(公告)号：US20150001710A1

公开(公告)日：2015-01-01

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Ying-Nan WEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。

公开(公告)号：US08916420B2

公开(公告)日：2014-12-23

申请号：US13900494

申请日：2013-05-22

Applicant: Xintec Inc.

Inventor： Baw-Ching Perng ,  Chun-Lung Huang

IPC: H01L23/433 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/433 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00

Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

Abstract translation: 一个实施例提供了一种芯片封装，其包括基板，从基板的上表面向下延伸的空腔，覆盖基板并保形地覆盖空腔的侧壁和底部的金属层，具有上表面并位于 所述空腔中的所述金属层，其中所述上表面不低于所述空腔外部的所述金属层的上表面，并且所述保护层覆盖所述芯片。