公开(公告)号：US11693585B2

公开(公告)日：2023-07-04

申请号：US17353349

申请日：2021-06-21

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/1018 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US11630789B2

公开(公告)日：2023-04-18

申请号：US17246311

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US20230063331A1

公开(公告)日：2023-03-02

申请号：US17676668

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/324 ,  G06F1/3206

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

公开(公告)号：US20230053530A1

公开(公告)日：2023-02-23

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F15/78 ,  G06F13/16 ,  G06F13/40

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11567861B2

公开(公告)日：2023-01-31

申请号：US17519284

申请日：2021-11-04

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/1045

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US11442528B2

公开(公告)日：2022-09-13

申请号：US17195362

申请日：2021-03-08

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brad W. Simeral ,  Lior Zimet

IPC: G06F1/3234 ,  G06F1/3293 ,  G06F1/329

Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

公开(公告)号：US20210191499A1

公开(公告)日：2021-06-24

申请号：US17195362

申请日：2021-03-08

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brad W. Simeral ,  Lior Zimet

IPC: G06F1/3234 ,  G06F1/3293 ,  G06F1/329

Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.